博通BCM4751 GPS接收芯片技术规格解析

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“博通GPS接收芯片BCM4751的datasheet提供了该芯片的详细技术规格和功能描述。” 博通BCM4751是一款集成化的单片GPS接收器集成电路，设计用于在主机系统中与CPU协同工作，实现高效的GPS信号处理。这款芯片的主要特点是采用了基于主机的集成架构，将处理功能划分为GPS芯片和主机CPU之间，以优化性能和降低对主机资源的需求。 BCM4751与博通的现有GPS解决方案——BCM4750兼容，确保了软件的互操作性。在功能分配上，BCM4751承担大部分计算密集型操作，而主机软件则负责执行可能受到载波和平台特定要求影响的最终计算。这种设计大大减轻了主机CPU的负担，无需实时处理要求，使得系统运行更加高效。博通提供了GPS定位库软件API，为设计者提供了无限制的访问权限，可以充分利用BCM4751的高级功能。这使得开发者能够更灵活地定制和优化GPS应用，以满足不同场景和需求。在封装方面，BCM4751提供了一种节省空间的封装选项，采用0.4mm球间距、2.9x3.1mm的WLBGA（晶圆级球栅阵列）封装，适用于板上芯片或模块应用。此外，还有0.65mm球间距的FBGA（方块扁平无引脚封装）供选择，以适应不同的设计和安装需求。在特性列表中，BCM4751可能包括但不限于以下几点： 1. 高度集成的GPS核心，支持多种导航系统。 2. 低功耗设计，适用于移动和便携式设备。 3. 强大的信号处理能力，能快速锁定卫星信号。 4. 支持AGC（自动增益控制）和PLL（锁相环）以适应不同环境的信号强度。 5. 内置温度传感器和电压监控，确保在各种环境条件下的稳定工作。 6. 提供丰富的接口选项，如I2C、SPI或UART，方便与主机系统的通信。 7. 具有抗干扰能力和错误检测机制，提高定位精度和可靠性。 BCM4751的datasheet会详细列出电气特性、机械尺寸、引脚配置、推荐的工作条件以及测试条件等，是设计者进行硬件设计和软件开发的重要参考资料。通过深入理解和应用这些信息，设计者可以构建出高性能、低功耗且具有高度灵活性的GPS解决方案。

2/28/2011 V5B5K

Table of Contents BCM4751 Data Sheet

BROADCOM

January 28, 2011 • 4751-DS10-R Page 9

Section 6: Host Transport and Bus Interfaces................................................................... 33

Transport Overview......................................................................................................................................33

UART .............................................................................................................................................................33

C..................................................................................................................................................................34

Section 7: Pin-Outs and Signal Descriptions..................................................................... 35

I/O States......................................................................................................................................................40

FBGA Ballout.................................................................................................................................................41

WLBGA Ballout .............................................................................................................................................42

Section 8: Electrical Characteristics.................................................................................. 43

Absolute Maximum Ratings.........................................................................................................................43

Recommended Operating Conditions..........................................................................................................44

I/O Digital Specifications..............................................................................................................................45

Maximum Current Consumption ...........................................................................................................46

C-Compatible Host Interface Specifications ........................................................................................47

Section 9: Mechanical Specifications ............................................................................... 49

Section 10: Ordering Information .................................................................................... 51

2/28/2011 V5B5K

List of Figures BCM4751 Data Sheet

BROADCOM

January 28, 2011 • 4751-DS10-R Page 10

List of Figures

Figure 1: Functional Block Diagram....................................................................................................................1

Figure 2: BCM4751 Block Diagram ...................................................................................................................13

Figure 3: BCM4751 GPS Radio Architecture.....................................................................................................14

Figure 4: Precision Time Transfer.....................................................................................................................17

Figure 5: Frequency Calibration Process ..........................................................................................................17

Figure 6: POR Timing Sequence for Systems Using the Pre-LDO .....................................................................19

Figure 7: POR Timing Sequence for Systems in Bypass Mode..........................................................................19

Figure 8: BCM4751 Top-Level PMU Diagram ...................................................................................................20

Figure 9: PMU Configuration with the Pre-LDO Regulator Provided by VBAT (Non_Bypass Mode) ...............22

Figure 10: PMU Configuration with VDD_PRE Supplied by an External Regulator (Bypass Mode)..................23

Figure 11: BCM4751 Power Sequencing Block Diagram ..................................................................................25

Figure 12: BCM4751 Top-Level Clocking Diagram............................................................................................26

Figure 13: TCXO Waveform ..............................................................................................................................27

Figure 14: Local GPS TCXO with a Reference Clock for Calibration..................................................................29

Figure 15: Shared TCXO with Software Calibration..........................................................................................30

Figure 16: Internal DC-Block and ESD Circuit ...................................................................................................31

Figure 17: BCM4751 FBGA Ballout Array (Top View) .......................................................................................41

Figure 18: BCM4751 WLBGA Ballout Array (Top View)....................................................................................42

Figure 19: I

C-Compatible Timing Diagram ......................................................................................................48

Figure 20: Outline Dimensions for the BCM4751 WLBGA 42-Pin Package ......................................................49

Figure 21: Outline Dimensions for the BCM4751 FBGA 100-Pin Package........................................................50

2/28/2011 V5B5K

List of Tables BCM4751 Data Sheet

BROADCOM

January 28, 2011 • 4751-DS10-R Page 11

List of Tables

Table 1: BCM4751 Required Power Supply Inputs...........................................................................................21

Table 2: Regulator Output Characteristics .......................................................................................................21

Table 3: BCM4751 Power Modes .....................................................................................................................21

Table 4: GPS TCXO Requirements ....................................................................................................................27

Table 5: Phase Noise Requirements for the BCM4751 Reference Frequency .................................................28

Table 6: GPS Calibration Clock Requirements ..................................................................................................31

Table 7: External LPO Clock Requirements ......................................................................................................32

Table 8: BCM4751 I

C-Compatible Controllers ................................................................................................34

Table 9: BCM4751 Pinouts ...............................................................................................................................35

Table 10: I/O States ..........................................................................................................................................40

Table 11: Pull-Up/Pull-Down Values ................................................................................................................41

Table 12: Absolute Maximum Ratings..............................................................................................................43

Table 13: Recommended Operating Conditions ..............................................................................................44

Table 14: BCM4751 I/O Digital Specifications ..................................................................................................45

Table 15: DC Characteristics—Current .............................................................................................................46

Table 16: I

C-Compatible Timing Specifications...............................................................................................47

Table 17: Ordering Information .......................................................................................................................51

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