Amphion MPEG2解码器原理与应用设计详解

需积分: 9 34 浏览量更新于2024-09-06 收藏 343KB PDF 举报

MPEG2 Decoder 原理图是Amphion公司针对高清晰度视频解码器市场推出的一款应用特定核心芯片——CS6650的设计图纸。这款解码器专为满足广泛的运动图像应用需求而设计，遵循ISO/IEC 13818-2（MPEG2）标准，支持高达4:2:2 Profile的高级别解码（422@HL）。它不仅适用于主流消费电子设备，能够处理4:2:0位流的高或主要级别编码（MP@HL），还兼容MPEG1（ISO/IEC 11172-2）编码的解码。该解码器的核心结构包括以下几个关键模块： 1. **Host Interface**: 用于与外部处理器（如微处理器）进行通信，允许数据交换和控制信号的传输，确保系统的稳定集成。 2. **Video Stream Parser**: 分析输入的视频数据流，将其分解成便于解码的各个部分，执行帧同步和错误检测等功能。 3. **Input Video Data Stream**: 输入的原始MPEG2视频数据，包含视频图像、音频以及其他相关信息。 4. **Frame Store**: 存储解码后的帧，以便在需要时提供连续的视频输出。 5. **SDRAMs**: 高速存储器，用于临时存储数据和优化解码性能，减少CPU访问延迟。 6. **Output Picture Data**: 解码后的视频数据，输出为清晰的像素信息，可供显示或进一步处理。 7. **Motion Compensation**: 通过预测和补偿技术来减少视频序列中的运动失真，提高画面流畅度。 8. **Variable Length Code Decoder**: 处理MPEG2压缩编码中的可变长度编码，实现高效的数据压缩和解压。 9. **Run Level Decoder**: 解码并解析编码中的运行长度（Run-Length）信息，这是MPEG2编码中的一种压缩方法。 10. **Microprocessor Interface**: 与微处理器协同工作，控制解码过程和处理解码后的数据。 CS6650的优势在于其高度集成，提供了卓越的性能，同时注重降低功耗和减小硅片面积，这使得它成为在消费电子、家庭娱乐系统、卫星接收器等应用领域中理想的解码解决方案。对于系统设计师来说，这份原理图提供了宝贵的设计参考，可以帮助他们理解和优化自己的硬件系统，以实现高效的MPEG2视频解码功能。

The Frame Store is implemented using two SDRAM chips

which are commodity PC133 64Mbit parts, each with 2Mx32

organization. The memory interface runs at 133MHz and can

be directly connected to the SDRAM chips using suitable

pads.

The Frame Store SDRAM Interface handles the mapping of

pixel read and write requests from the Motion Compensation,

Picture Reconstruction and Picture DMA units into linear

memory addresses. Additionally, the host interface can access

the memory banks. Arbitration between the various accessing

units and memory transaction queues are all maintained by

the SDRAM Interface.

PICTURE DISPLAY DMA

The Picture Display DMA has a double-byte output interface

which can carry Y, Cr or Cb pixel data. Y and Cr or Cb data

can be output simultaneously as 16-bit wide values or

sequentially as four separate bytes. For 4:2:0 video streams the

Picture Display DMA unit will upsample the chrominance

vertically to provide a 4:2:2 output. The Display DMA engine

has the capability to be programmed by the host CPU to

display only a certain portion of the picture or, in stand-alone

mode, will display the entire coded picture.

A number of handshake signals are provided on the Picture

Display DMA interface to allow the external logic to control

the timing of the pixel output stream and to control the end of

the current scan row or picture display. Outputs indicate to

the external logic the nature of the pixel being currently

driven; the end of row and end of picture flags are available to

allow, for example, sync pulse generation.

HOST INTERFACE

When the CS6650 is operating with the assistance of a host

CPU, a number of additional features can be accessed. All

interfacing between the host and the CS6650 is performed

through the Host Interface unit. This unit allows read/write

access to all the internal control, status and video stream

parameter registers contained within the decoder.

The Host Interface also provides a simple 32-bit read/write

access to the Frame Store SDRAM. Normally, the areas of the

SDRAM used for storage of picture data cannot be accessed

by the Host Interface; however, a bypass mode allowing direct

access is provided for system diagnostic tests, etc.

A number of conditions arising from the decoding of the

video stream may require the software on the CPU to be

alerted. An interrupt controller within the Host Interface unit

provides a simple Interrupt Request signal and an interrupt

status and mask register.

Figure 2: CS6650 Symbol and Pin Description

Clk

SD_DataOut(63:0)

SD_DQM(7:0)

SD_Addr(10:0)

SD_BA(1:0)

P_Data(15:0)

P_DataAvail

P_DataType(3:0)

P_DataStrobe

P_RowDoneOut

P_PicDoneOut

P_RowDoneIn

P_PicDoneIn

P_General(7:0)

SD_notRAS

SD_notCAS

SD_notWE

SD_notCS

notReset

CoreReset

ES_Data(7.0)

ES_Valid

ES_Stall

H_DataOut(31:0)

H_DataIn(31:0)

H_notDatDrv

H_Addr(21:0)

H_notRegCS

H_notWrite

H_notMemRead

H_notMemWrite

H_MemBusy

H_ByteEnable(3:0)

H_MemRdValid

H_MemRdStrb

H_MemWrValid

H_MemWrReady

H_notIRQ

SD_DataIn(63:0)

SD_notDatDrv

Table 1: Global Signals

Signal I/O Description

Clk I Core Clock. Master clock used for all logic and the external SDRAM interface. This clock should also be

routed to the external SDRAM chips. This clock should be 133 MHz.

notReset I Core reset. Asynchronous, active low global core reset

CoreReset I Core reset. Synchronous, active high core reset

剩余11页未读，继续阅读

drjiachen

粉丝: 172
资源: 2138

Amphion MPEG2解码器原理与应用设计详解

mpeg2.rar_mpeg2_mpeg2 decoder code_mpeg2 encoder_verify

mpeg2 decoder filter

MPEG2标准介绍MPEG2标准介绍

MPEG2基础和协议分析指南

DSP芯片的图像采集处理系统

MPEG-2音视频同步技术原理及应用

基于java的贝儿米幼儿教育管理系统答辩PPT.pptx

课设毕设基于SpringBoot+Vue的养老院管理系统的设计与实现源码可运行.zip

基于java的消防物资存储系统答辩PPT.pptx

【java毕业设计】饮食营养管理信息系统源码（springboot+vue+mysql+说明文档）.zip

最新资源