16 Intel Confidential 546717
17-2 eSPI Virtual Wires (VW)........................................................................................127
18-1 GPIO Group Summary.......................................................................................... 133
18-2 General Purpose I/O Signals.................................................................................. 134
18-3 PWM Output Frequencies Assuming 32.768 KHz....................................................... 146
21-1 GbE LAN Signals.................................................................................................. 161
21-2 Integrated Pull-Ups and Pull-Downs ....................................................................... 162
21-3 Power Plane and States for Output Signals ..............................................................162
21-4 Power Plane and States for Input Signals ................................................................ 162
21-5 LAN Mode Support ...............................................................................................166
22-1 Interrupt Options - 8259 Mode .............................................................................. 168
22-2 Interrupt Options - APIC Mode............................................................................... 169
22-3 Interrupt Logic Signals ......................................................................................... 170
22-4 Interrupt Controllers PIC ...................................................................................... 171
22-5 Interrupt Status Registers.....................................................................................172
22-6 Content of Interrupt Vector Byte............................................................................ 172
22-7 APIC Interrupt Mapping1 ......................................................................................178
22-8 Stop Frame Explanation........................................................................................ 180
22-9 Data Frame Format.............................................................................................. 181
23-1 IPC Initiator -> Target flows .................................................................................186
24-1 LPC Cycle Types Supported................................................................................... 190
24-2 Start Field Bit Definitions ...................................................................................... 191
24-3 Cycle Type Bit Definitions .....................................................................................191
24-4 Transfer Size Bit Definition.................................................................................... 192
24-5 SYNC Bit Definition ..............................................................................................192
25-1 I/O Signal Planes and States ................................................................................. 196
26-1 PCI Express* Port Feature Details ..........................................................................200
26-2 PCI Express* Link Configurations Supported............................................................ 201
26-3 MSI Versus PCI IRQ Actions ..................................................................................202
27-1 General Power States for Systems Using the PCH..................................................... 214
27-2 State Transition Rules for the PCH ......................................................................... 215
27-3 System Power Plane............................................................................................. 216
27-4 Causes of SMI and SCI .........................................................................................217
27-5 Sleep Types ........................................................................................................ 220
27-6 Causes of Wake Events ........................................................................................221
27-7 Transitions Due to Power Failure............................................................................ 222
27-8 Supported Deep Sx Policy Configurations ................................................................ 223
27-9 Deep Sx Wake Events ..........................................................................................224
27-10 Transitions Due to Power Button............................................................................224
27-11 Write Only Registers with Read Paths in ALT Access Mode .........................................228
27-12 PIC Reserved Bits Return Values............................................................................229
27-13 Register Write Accesses in ALT Access Mode............................................................ 229
27-14 SUSPWRDNACK/SUSWARN#/GPP_A13 Pin Behavior ................................................. 233
27-15 SUSPWRDNACK During Reset................................................................................233
27-16 Causes of Host and Global Resets .......................................................................... 235
28-1 RTC Crystal Requirements .................................................................................... 240
28-2 External Crystal Oscillator Requirements................................................................. 240
31-1 I
2
C* Block Read ..................................................................................................267
31-2 Enable for SMBALERT#......................................................................................... 270
31-3 Enables for SMBus Slave Write and SMBus Host Events ............................................270
31-4 Enables for the Host Notify Command ....................................................................270
31-5 Slave Write Registers ........................................................................................... 272
31-6 Command Types..................................................................................................272
31-7 Slave Read Cycle Format ...................................................................................... 273
31-8 Data Values for Slave Read Registers .....................................................................273
31-9 Host Notify Format ..............................................................................................276