PC16550D
SNLS378C –JUNE 1995–REVISED MAY 2015
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN MAX UNIT
All input or output voltages with respect to V
SS
–0.5 7 V
Power Dissipation 1 W
Storage temperature, T
stg
–65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
V
(ESD)
Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22- ±1500
C101
(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
T
A
Ambient Temperature 0 25 70 °C
V
DD
Supply Voltage 4.5 5 5.5 V
7.4 Electrical Characteristics
T
A
= 0°C to 70°C, V
DD
= 5 V ± 10%, V
SS
= 0 V, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
ILX
Clock input low voltage –0.5 0.8 V
V
IHX
Clock input high voltage 2.0 V
DD
V
V
IL
Input low voltage –0.5 0.8 V
V
IH
Input high voltage 2 V
DD
V
V
OL
Output low voltage I
OL
= 1.6 mA on all
(1)
0.4 V
V
OH
Output high voltage I
OH
= –1.0 mA
(1)
2.4 V
V
DD
= 5.5 V, T
A
= 25°C, No Loads on output,
I
CC
(AV) Average power supply current SIN, DSR, DCD, CTS, RI = 2.0 V, 15 mA
All other inputs = 0.8 V
I
IL
Input leakage ±10 mA
V
DD
= 5.5 V, V
SS
= 0 V, All other pins floating,
V
IN
= 0 V, 5.5 V
I
CL
Clock leakage ±10 mA
V
DD
= 5.5 V, V
SS
= 0 V, V
OUT
= 0 V, 5.25 V
I
OZ
TRI-STATE leakage 1) Chip deselected ±20 mA
2) WRITE mode, chip selected
V
ILMR
MR Schmitt V
IL
0.8 V
V
IHMR
MR Schmitt V
IH
2 V
CAPACITANCE: T
A
= 25°C, V
DD
= V
SS
= 0 V
C
XIN
Clock input capacitance 7 9 pF
C
XOUT
Clock output capacitance 7 9 pF
C
IN
Input capacitance f
c
= 1 MHz, Unmeasured pins returned to V
SS
5 7 pF
C
OUT
Output capacitance 6 8 pF
C
I/O
Input/Output capacitance 10 12 pF
(1) Does not apply to XOUT.
8 Submit Documentation Feedback Copyright © 1995–2015, Texas Instruments Incorporated
Product Folder Links: PC16550D
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