RISC-V最新版特权架构手册：2019年6月发布

RISC-V

特权指令集

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RISC-V指令集是开放源代码的精简指令集架构(Reduced Instruction Set Computing, RISC)，其最新版本的《RISC-V指令集手册第二卷：特权架构》(The RISC-V Instruction Set Manual Volume II: Privileged Architecture)于2019年6月8日发布。该手册由Andrew Waterman和Krste Asanović主导，来自SiFive Inc.和加州大学伯克利分校电子工程与计算机科学系的CSDivision团队共同编撰。文档旨在详细阐述RISC-V架构中的特权指令集，这是RISC-V体系结构的核心部分，提供了对硬件底层操作的访问权限，包括处理器控制、中断处理、内存管理等高级功能。 RISC-V的特权指令集主要包括以下几个关键方面： 1. **系统控制**：这部分提供了对操作系统内核运行的控制，如设置时钟频率、管理异常处理程序（如陷阱和中断），以及支持多任务和多线程的上下文切换。 2. **内存管理单元(Memory Management Unit, MMU)**：特权指令集定义了与内存管理相关的操作，如地址空间布局、虚拟地址到物理地址的转换，以及内存保护机制，确保了数据安全和内存隔离。 3. **中断管理**：通过特权指令，程序员可以配置和响应不同类型的中断，如外部中断（如定时器或I/O设备）、内部中断（如处理器状态改变）以及软件中断（用于调试目的）。 4. **异常处理**：处理未定义指令、除零错误、内存访问错误等异常情况，这些异常通常导致处理器进入特权模式，并执行相应的恢复操作。 5. **处理器状态和寄存器**：特权指令集定义了处理器状态寄存器（如程序计数器PC、通用寄存器等）的读写操作，以及与处理器模式切换相关的操作。 6. **系统配置和扩展**：允许开发者自定义硬件特性，如ISA扩展、存储器映射和I/O控制器的配置，从而支持定制化的RISC-V实现。该手册的贡献者列表显示了RISC-V社区的广泛参与，涵盖了学术界和工业界的专家。RISC-V的开放性和灵活性使得它在全球范围内得到了广泛关注，特别在嵌入式系统、物联网、云计算等领域具有巨大的潜力。随着RISC-V的发展，这份文档持续更新和完善，以适应不断增长的技术需求。《RISC-V指令集手册第二卷：特权架构》是理解RISC-V技术精髓的关键资源，对于开发人员、架构设计师和研究者来说，它是深入探索RISC-V系统设计和优化的基石。随着RISC-V生态系统的不断壮大，这一文档的重要性将只会增加。

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4 Volume II: RISC-V Privileged Architectures V20190608-Priv-MSU-Ratiﬁed

A hart normally runs application code in U-mode until some trap (e.g., a supervisor call or a timer

interrupt) forces a switch to a trap handler, which usually runs in a more privileged mode. The hart

will then execute the trap handler, which will eventually resume execution at or after the original

trapped instruction in U-mode. Traps that increase privilege level are termed vertical traps, while

traps that remain at the same privilege level are termed horizontal traps. The RISC-V privileged

architecture provides ﬂexible routing of traps to diﬀerent privilege layers.

Horizontal traps can be implemented as vertical traps that return control to a horizontal trap

handler in the less-privileged mode.

1.3 Debug Mode

Implementations may also include a debug mode to support oﬀ-chip debugging and/or manufac-

turing test. Debug mode (D-mode) can be considered an additional privilege mode, with even more

access than M-mode. The separate debug speciﬁcation proposal describes operation of a RISC-V

hart in debug mode. Debug mode reserves a few CSR addresses that are only accessible in D-mode,

and may also reserve some portions of the physical address space on a platform.

Chapter 2

Control and Status Registers (CSRs)

The SYSTEM major opcode is used to encode all privileged instructions in the RISC-V ISA. These

can be divided into two main classes: those that atomically read-modify-write control and status

registers (CSRs), and all other privileged instructions. In addition to the user-level state described

in Volume I of this manual, an implementation may contain additional CSRs, accessible by some

subset of the privilege levels using the CSR instructions described in the user-level manual. In

this chapter, we map out the CSR address space. The following chapters describe the function of

each of the CSRs according to privilege level, as well as the other privileged instructions which

are generally closely associated with a particular privilege level. Note that although CSRs and

instructions are associated with one privilege level, they are also accessible at all higher privilege

levels.

2.1 CSR Address Mapping Conventions

The standard RISC-V ISA sets aside a 12-bit encoding space (csr[11:0]) for up to 4,096 CSRs.

By convention, the upper 4 bits of the CSR address (csr[11:8]) are used to encode the read and

write accessibility of the CSRs according to privilege level as shown in Table 2.1. The top two bits

(csr[11:10]) indicate whether the register is read/write (00, 01, or 10) or read-only (11). The next

two bits (csr[9:8]) encode the lowest privilege level that can access the CSR.

The CSR address convention uses the upper bits of the CSR address to encode default access

privileges. This simpliﬁes error checking in the hardware and provides a larger CSR space, but

does constrain the mapping of CSRs into the address space.

Implementations might allow a more-privileged level to trap otherwise permitted CSR ac-

cesses by a less-privileged level to allow these accesses to be intercepted. This change should be

transparent to the less-privileged software.

Attempts to access a non-existent CSR raise an illegal instruction exception. Attempts to access a

CSR without appropriate privilege level or to write a read-only register also raise illegal instruction

exceptions. A read/write register might also contain some bits that are read-only, in which case

writes to the read-only bits are ignored.

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RISC-V最新版特权架构手册：2019年6月发布

riscv-privileged-spec-v1.7中文版

The RISC-V Instruction Set Manual Volume I-Unprivileged ISA V20180801-draft

The RISC-V Instruction Set Manual Volume II: Privileged Architecture 1.10

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