高性能SC16IS750/760 UART接口芯片：I2C/SPI转RS-232/485接口

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SC16IS740/750/760是一款专为高数据速率通信设计的单通道高性能UART接口芯片，旨在满足I2C总线和SPI协议到串行通信（如RS-232/RS-485）之间的无缝转换需求。这款设备的最大优势在于其高速数据传输能力，SC16IS750和SC16IS760支持高达5Mbit/s的数据速率，这在手持设备或电池供电应用中具有显著优势，考虑到它们的小巧外形，如HVQFN24、TSSOP24（SC16IS750/760）和TSSOP16（SC16IS740）封装。 SC16IS750和SC16IS760的区别主要体现在接口速度上：SC16IS750支持4Mbit/s的SPI时钟，而SC16IS760则提升到了15Mbit/s，使其在处理高速数据流时更具竞争力。此外，SC16IS760还具备对IrDA红外数据通信（IrDA）的支持，最大速率为1.152Mbit/s，进一步扩展了其功能范围。 SC16IS740与SC16IS750在功能和电气特性上完全相同，只是不具备可编程I/O引脚，这是SC16IS750特有的特性。内部寄存器集设计为兼容广泛使用的UART标准，这意味着开发者可以轻松集成这些设备到现有的系统中，而无需担心兼容性问题。 SC16IS740/750/760系列提供了高效、低功耗的解决方案，适用于对数据传输速度、小型化和灵活性有高要求的应用场景，无论是工业控制、物联网设备还是消费电子，都能找到其适用之处。在选择时，开发者应根据实际需求，考虑数据速率、I/O选项以及封装类型来决定最适合的型号。

Product data sheet Rev. 05 — 16 November 2006 11 of 62

NXP Semiconductors

SC16IS740/750/760

Single UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7.2.2 Auto CTS

Figure 10 shows CTS functional timing. The transmitter circuitry checks CTS before

sending the next data byte. When CTS is active, the transmitter sends the next byte. To

stop the transmitter from sending the following byte, CTS must be deasserted before the

middle of the last stop bit that is currently being sent. The auto CTS function reduces

interrupts to the host system. When ﬂow control is enabled, CTS level changes do not

trigger host interrupts because the device automatically controls its own transmitter.

Without auto CTS, the transmitter sends any data present in the transmit FIFO and a

receiver overrun error may result.

7.3 Software ﬂow control

Software ﬂow control is enabled through the enhanced feature register and the Modem

Control Register. Different combinations of software ﬂow control can be enabled by setting

different combinations of EFR[3:0]. Table 3 shows software ﬂow control options.

(1) When CTS is LOW, the transmitter keeps sending serial data out.

(2) When CTS goes HIGH before the middle of the last stop bit of the current character, the transmitter ﬁnishes sending the

current character, but it does not send the next character.

(3) When CTS goes from HIGH to LOW, the transmitter begins sending data again.

Fig 10. CTS functional timing

start bit 0 to bit 7 stopTX

CTS

002aab041

start stop

bit 0 to bit 7

Table 3. Software ﬂow control options (EFR[3:0])

EFR[3] EFR[2] EFR[1] EFR[0] TX, RX software ﬂow control

0 0 X X no transmit ﬂow control

1 0 X X transmit Xon1, Xoff1

0 1 X X transmit Xon2, Xoff2

1 1 X X transmit Xon1 and Xon2, Xoff1 and Xoff2

X X 0 0 no receive ﬂow control

X X 1 0 receiver compares Xon1, Xoff1

X X 0 1 receiver compares Xon2, Xoff2

1011transmit Xon1, Xoff1

receiver compares Xon1 or Xon2, Xoff1 or Xoff2

0111transmit Xon2, Xoff2

receiver compares Xon1 or Xon2, Xoff1 or Xoff2

1111transmit Xon1 and Xon2, Xoff1 and Xoff2

receiver compares Xon1 and Xon2, Xoff1 and Xoff2

0011no transmit ﬂow control

receiver compares Xon1 and Xon2, Xoff1 and Xoff2

Product data sheet Rev. 05 — 16 November 2006 12 of 62

NXP Semiconductors

SC16IS740/750/760

Single UART with I

C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

There are two other enhanced features relating to software ﬂow control:

• Xon Any function (MCR[5]): Receiving any character will resume operation after

recognizing the Xoff character. It is possible that an Xon1 character is recognized as

an Xon Any character, which could cause an Xon2 character to be written to the RX

FIFO.

• Special character (EFR[5]): Incoming data is compared to Xoff2. Detection of the

special character sets the Xoff interrupt (IIR[4]) but does not halt transmission. The

Xoff interrupt is cleared by a read of the IIR. The special character is transferred to the

RX FIFO.

7.3.1 RX

When software ﬂow control operation is enabled, the SC16IS740/750/760 will compare

incoming data with Xoff1/Xoff2 programmed characters (in certain cases, Xoff1 and Xoff2

must be received sequentially). When the correct Xoff characters are received,

transmission is halted after completing transmission of the current character. Xoff

detection also sets IIR[4] (if enabled via IER[5]) and causes IRQ to go LOW.

To resume transmission, an Xon1/Xon2 character must be received (in certain cases

Xon1 and Xon2 must be received sequentially). When the correct Xon characters are

received, IIR[4] is cleared, and the Xoff interrupt disappears.

7.3.2 TX

Xoff1/Xoff2 character is transmitted when the RX FIFO has passed the HALT trigger level

programmed in TCR[3:0] or the selectable trigger level in FCR[7:6]

Xon1/Xoff2 character is transmitted when the RX FIFO reaches the RESUME trigger level

programmed in TCR[7:4] or RX FIFO falls below the lower selectable trigger level in

FCR[7:6].

The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an

ordinary character from the FIFO. This means that even if the word length is set to be 5, 6,

or 7 bits, then the 5, 6, or 7 least signiﬁcant bits of XOFF1/XOFF2 or XON1/XON2 will be

transmitted. (Note that the transmission of 5, 6, or 7 bits of a character is seldom done, but

this functionality is included to maintain compatibility with earlier designs.)

It is assumed that software ﬂow control and hardware ﬂow control will never be enabled

simultaneously. Figure 11 shows an example of software ﬂow control.

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