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ECCN 5E002 TSPA - Technology / Software Publicly Available.
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9-4 Port Mapping Registers for Port Px – Word Access ................................................................. 302
10-1 DMA Transfer Modes..................................................................................................... 309
10-2 DMA Trigger Operation .................................................................................................. 315
10-3 Maximum Single-Transfer DMA Cycle Time .......................................................................... 316
10-4 DMA Registers ............................................................................................................ 319
11-1 Result Availability (MPYFRAC = 0, MPYSAT = 0) ................................................................... 332
11-2 OP1 Registers ............................................................................................................. 334
11-3 OP2 Registers ............................................................................................................. 334
11-4 SUMEXT and MPYC Contents.......................................................................................... 335
11-5 Result Availability in Fractional Mode (MPYFRAC = 1, MPYSAT = 0) ............................................ 337
11-6 Result Availability in Saturation Mode (MPYSAT = 1) ............................................................... 338
11-7 MPY32 Registers ......................................................................................................... 345
11-8 Alternative Registers ..................................................................................................... 347
12-1 CRC Module Registers ................................................................................................... 354
13-1 AES Accelerator Registers .............................................................................................. 364
14-1 Timer Modes .............................................................................................................. 372
14-2 Output Modes ............................................................................................................. 378
14-3 Timer_A Registers ........................................................................................................ 384
15-1 Real-Time Clock Registers .............................................................................................. 397
16-1 Receive Error Conditions ................................................................................................ 418
16-2 BITCLK Modulation Pattern ............................................................................................. 420
16-3 BITCLK16 Modulation Pattern .......................................................................................... 421
16-4 Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 0 ................................................. 424
16-5 Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 1 ................................................. 426
16-6 USCI_Ax Registers ....................................................................................................... 429
17-1 UCxSTE Operation ....................................................................................................... 441
17-2 USCI_Ax Registers ....................................................................................................... 446
17-3 USCI_Bx Registers ....................................................................................................... 446
18-1 I
2
C State Change Interrupt Flags ....................................................................................... 471
18-2 USCI_Bx Registers ....................................................................................................... 473
19-1 One-Byte Auto-Read Registers ......................................................................................... 487
19-2 Two-Byte/One-Word Auto-Read Registers ............................................................................ 487
19-3 Radio Interface Error Conditions ........................................................................................ 488
19-4 Radio Interface Interrupt Flags .......................................................................................... 489
19-5 CC1101 Radio Core Interrupt Mapping ................................................................................ 490
19-6 CC1101-Based Radio Core Instruction Set – Command Strobes .................................................. 495
19-7 CC1101-Based Radio Core Instruction Set ........................................................................... 496
19-8 Radio Core Status Byte Summary ...................................................................................... 497
19-9 Data Rate Step Size ...................................................................................................... 498
19-10 Channel Filter Bandwidths (kHz) (Assuming a 26-MHz Crystal) .................................................. 498
19-11 Received Packet Status Byte 1 (First Byte Appended After Data) ................................................. 500
19-12 Received Packet Status Byte 2 (Second Byte Appended After Data) ............................................. 500
19-13 Symbol Encoding for 2-FSK/2-GFSK Modulation .................................................................... 505
19-14 Sync Word Qualifier Mode ............................................................................................... 506
19-15 Typical RSSI_offset Values ............................................................................................. 507
19-16 Typical RSSI Value in dBm at CS Threshold With Default MAGN_TARGET at 2.4 kBaud, 868 MHz ........ 509
19-17 Typical RSSI Value in dBm at CS Threshold With Default MAGN_TARGET at 250 kBaud, 868 MHz ....... 510
19-18 State Transition Timing .................................................................................................. 514
19-19 FIFO_THR Settings and the Corresponding FIFO Thresholds ..................................................... 515
19-20 Configuration Registers .................................................................................................. 523
19-21 Status Registers .......................................................................................................... 524
16 List of Tables SLAU259 – May 2009
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