ATmega328P微控制器数据手册：高性能低功耗AVR 8位微控制器

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"Atmel ATmega328P 微控制器数据手册" 本资源为 Atmel ATmega328P 微控制器的数据手册，提供了该微控制器的详细信息和技术参数。该手册来自 Arduino 官方网站，更新日期为 2020 年 1 月 22 日。 **微控制器概述** ATmega328P 是一款高性能、低功率的 8 位微控制器，基于 AVR 架构。它具有高达 16MIPS 的处理速度，拥有 32 个 8 位通用寄存器和一个 2 周期乘法器。该微控制器还具有高耐用性的非易失存储器，包括 32KB 的 Flash 程序存储器、1KB 的 EEPROM 和 2KB 的内部 SRAM。 **存储器结构** ATmega328P 的存储器结构包括 Flash 程序存储器、EEPROM 和 SRAM。Flash 程序存储器可以通过 ISP（In-System Programming）方式进行编程和擦除，具有 10,000 次写入/擦除周期。EEPROM 具有 100,000 次写入/擦除周期。SRAM 用于存储数据和程序。 **定时器和计数器** ATmega328P 微控制器具有多种定时器和计数器，包括两个 8 位定时器/计数器、一个 16 位定时器/计数器和一个实时计数器。这些定时器和计数器可以用于生成时钟信号、计数事件和测量时间间隔等。 **模拟数字转换器** ATmega328P 微控制器具有一个 8 通道 10 位模拟数字转换器（ADC），可以将模拟信号转换为数字信号。 **串行通信** ATmega328P 微控制器具有多种串行通信接口，包括 USART、SPI 和 I2C。USART 是一种通用异步收发器，可以进行串行数据传输。SPI 是一种高速串行通信协议，用于与外部设备进行数据交换。I2C 是一种总线式串行通信协议，用于与外部设备进行数据交换。 **其他特性** ATmega328P 微控制器还具有多种其他特性，包括温度测量、真实读写操作、编程锁和 bootloader。温度测量功能可以用于测量微控制器的温度。真实读写操作可以在不中断程序执行的情况下进行数据读写。编程锁可以用于保护程序代码免受未经授权的访问。bootloader 是一种启动加载程序，用于加载应用程序到微控制器中。 Atmel ATmega328P 微控制器是款功能强大、性能优异的微控制器，广泛应用于自动化控制、机器人、物联网等领域。

ATmega328P [DATASHEET]

7810D–AVR–01/15

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed

after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can

be used to avoid interrupts during the timed EEPROM write sequence.

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending

interrupts, as shown in this example.

6.7.1 Interrupt Response Time

The interrupt execution response for all the enabled AVR

interrupts is four clock cycles minimum. After four clock cycles the

program vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the program

counter is pushed onto the stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock

cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is

served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four

clock cycles. This increase comes in addition to the start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the program counter (two

bytes) is popped back from the stack, the stack pointer is incremented by two, and the I-bit in SREG is set.

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMPE ; start EEPROM write

sbi EECR, EEPE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

_CLI();

EECR |= (1<<EEMPE); /* start EEPROM write */

EECR |= (1<<EEPE);

SREG = cSREG; /* restore SREG value (I-bit) */

Assembly Code Example

sei ; set Global Interrupt Enable

sleep ; enter sleep, waiting for interrupt

; note: will enter sleep before any pending interrupt(s)

C Code Example

__enable_interrupt(); /* set Global Interrupt Enable */

__sleep(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

ATmega328P [DATASHEET]

7810D–AVR–01/15

7.3 SRAM Data Memory

Figure 7-2 shows how the ATmega328P SRAM memory is organized.

The ATmega328P is a complex microcontroller with more peripheral units than can be supported within the 64 locations

reserved in the opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM, only the

ST/STS/STD and LD/LDS/LDD instructions can be used.

The lower 2303 data memory locations address both the register file, the I/O memory, extended I/O memory, and the

internal data SRAM. The first 32 locations address the register file, the next 64 location the standard I/O memory, then 160

locations of extended I/O memory, and the next 2048 locations address the internal data SRAM.

The five different addressing modes for the data memory cover: Direct, indirect with displacement, indirect, indirect with

pre-decrement, and indirect with post-increment. In the register file, registers R26 to R31 feature the indirect addressing

pointer registers.

The direct addressing reaches the entire data space.

The indirect with displacement mode reaches 63 address locations from the base address given by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X,

Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O registers, 160 extended I/O registers, and the 2048 bytes of internal data

SRAM in the ATmega328P are all accessible through all these addressing modes. The register file is described in

Section 6.4 “General Purpose Register File” on page 12.

Figure 7-2. Data Memory Map

7.3.1 Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The internal data SRAM access is

performed in two clk

CPU

cycles as described in Figure 7-3.

Figure 7-3. On-chip Data SRAM Access Cycles

32 Registers

Data Memory

0x0000 - 0x001F

0x0020 - 0x005F

0x0060 - 0x00FF

0x0100

0x08FF

64 I/O Registers

160 Ext I/O Registers

Internal SRAM

(1048 x 8)

clk

CPU

Data

Address validCompute Address

Next Instruction

Write

Read

Memory Access Instruction

ddress

T2 T3

ATmega328P [DATASHEET]

7810D–AVR–01/15

7.4 EEPROM Data Memory

The Atmel

ATmega328P contains 1Kbyte of data EEPROM memory. It is organized as a separate data space, in which

single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access

between the EEPROM and the CPU is described in the following, specifying the EEPROM address registers, the EEPROM

data register, and the EEPROM control register.

Section 27. “Memory Programming” on page 241 contains a detailed description on EEPROM programming in SPI or

parallel programming mode.

7.4.1 EEPROM Read/Write Access

The EEPROM access registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 7-2 on page 22. A self-timing function, however, lets the user

software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some

precautions must be taken. In heavily filtered power supplies, V

is likely to rise or fall slowly on power-up/down. This

causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used.

See Section 7.4.2 “Preventing EEPROM Corruption” on page 19 for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the

EEPROM control register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the

EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

7.4.2 Preventing EEPROM Corruption

During periods of low V

CC,

the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the

EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design

solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to

the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly,

if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the

internal brown-out detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an

external low V

reset protection circuit can be used. If a reset occurs while a write operation is in progress, the write

operation will be completed provided that the power supply voltage is sufficient.

7.5 I/O Memory

The I/O space definition of the ATmega328P is shown in Section “” on page 275.

All ATmega328P I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD

and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O

registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set

section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used.

When addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The

ATmega328P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved

in opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and

LD/LDS/LDD instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVR

, the CBI and SBI

instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The

CBI and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

ATmega328P [DATASHEET]

7810D–AVR–01/15

7.5.1 General Purpose I/O Registers

The Atmel

ATmega328P contains three general purpose I/O registers. These registers can be used for storing any

information, and they are particularly useful for storing global variables and status flags. General purpose I/O registers within

the address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

7.6 Register Description

7.6.1 EEARH and EEARL – The EEPROM Address Register

• Bits 15..9 – Res: Reserved Bits

These bits are reserved bits in the Atmel ATmega328P and will always read as zero.

• Bits 8..0 – EEAR8..0: EEPROM Address

The EEPROM address registers – EEARH and EEARL specify the EEPROM address in the 256/512/512/1K bytes

EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 255/511/511/1023. The initial value of

EEAR is undefined. A proper value must be written before the EEPROM may be accessed.

EEAR8 is an unused bit in ATmega328P and must always be written to zero.

7.6.2 EEDR – The EEPROM Data Register

• Bits 7..0 – EEDR7.0: EEPROM Data

For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by

the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address

given by EEAR.

7.6.3 EECR – The EEPROM Control Register

• Bits 7..6 – Res: Reserved Bits

These bits are reserved bits in the Atmel ATmega328P and will always read as zero.

• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits

The EEPROM programming mode bit setting defines which programming action that will be triggered when writing EEPE. It

is possible to program data in one atomic operation (erase the old value and program the new value) or to split the erase and

write operations in two different operations. The programming times for the different modes are shown in Table 7-1. While

EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is

busy programming.

Bit 151413121110 9 8

0x22 (0x42) –––––––EEAR8EEARH

0x21 (0x41) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

76543210

Read/Write R R R R R R R R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 X

XXXXXXXX

Bit 76543210

0x20 (0x40) MSB LSB EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

0x1F (0x3F) – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value 0 0 X X 0 0 X 0

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