JEDEC JESD96A.01-2023：无线电前端-基带（RF-BB）接口标准

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"JEDEC JESD96A.01-2023是无线电前端-基带（RF-BB）接口的标准文档，由JEDEC固态技术协会于2023年1月发布，是对2006年2月版本JESD96A的编辑性修订。该标准旨在通过消除制造商与购买者之间的误解，促进互换性和产品改进，帮助购买者在最短时间内选择并获取合适的产品，无论这些产品是在国内还是国际市场使用。" JEDEC（Joint Electron Device Engineering Council）是电子设备工程联合委员会的缩写，是一个国际性的行业组织，专注于制定半导体行业的标准和规范。JESD96A.01-2023标准是关于无线电前端与基带之间接口的一个重要规范，它定义了射频（Radio Front End）和基带（Baseband）系统之间通信的一系列技术要求、接口协议和性能指标。无线电前端是无线通信系统中的一个重要组成部分，主要负责处理无线信号的接收和发送，包括频率转换、放大、滤波等操作。基带部分则处理数字信号，执行调制、解调、编码、解码等功能。RF-BB接口是连接这两部分的关键，确保它们协同工作，高效地传输数据。在JESD96A.01-2023中，可能涉及的内容包括但不限于： 1. **接口规范**：定义了RF和BB模块之间的物理连接、电气特性，如电压等级、电流限制、信号线的阻抗匹配等，确保信号传输的准确性和稳定性。 2. **协议规定**：规定了数据传输的时序、控制信号、同步机制，以及错误检测和纠正策略，保证通信的可靠性。 3. **性能指标**：设定了一系列性能参数，如信号质量、带宽、功率效率、射频范围等，确保系统的整体性能满足设计要求。 4. **兼容性和互换性**：通过标准化接口，使得不同厂商的RF和BB组件能够相互配合，降低了系统集成的复杂性和成本。 5. **知识产权声明**：JEDEC标准不涉及任何专利问题，但使用标准可能会涉及到第三方的专利权，使用者需要自行处理相关授权问题。 6. **适用范围**：此标准适用于各种无线通信设备，包括移动电话、无线局域网设备、蓝牙设备等，促进了不同设备间的互通性。 JESD96A.01-2023标准对于设计和制造无线通信设备的工程师来说，是一份至关重要的参考文档，它提供了实现RF-BB接口标准化的框架和指南，有助于提高产品的互操作性和市场竞争力。同时，这个标准也对采购者提供了选择合适产品的重要依据。

JEDEC Standard No. 96A.01

Page 3

3 Terminology (cont’d)

3.1 Terms and definitions (cont’d)

big endian: The format in which the most significant bit (MSB) of a word is transferred first and the least

significant bit is transferred last.

TX_IN: Single-ended combination of TX/TXN analog signals received by FED.

TX_DATA_VALID (FED): Indication the TX_IN signal contains data for the FED Transport Layer.

TX_CLK: Clock signal from FED Link Layer to the FED Transport Layer that has been deskewed for maximum

data eye opening on TX_IN.

RX_OUT: Single-ended serial data from the FED Transport Layer to the FED Link Layer which is synchronized

with CLK_90.

RX_DATA_VALID (FED): Indication that the RX_OUT signal contains data for the FED Link layer.

CLK_90: 90-degree-offset clock signal provided by the FED Link Layer to the FED Transport layer to synchronize

outgoing RX_OUT.

LINK_REQUEST: Indication that the Transport layer requires FED Link Layer services. This could also serve as

a data clock request.

DESKEW_REQUEST: Indication that the Transport layer needs the Link to deskew incoming data and clocks.

One possible reason to send this is because of some CRC error seen in the Transport layer.

LINK_STATUS: This signal reports that the Link is ready, or not ready. It is related to DESKEW_STATUS as

well.

TX_CM_DET: Indication to the FED Link layer from the FED Electrical layer that a minimum active common

mode voltage has been detected on the TX/TXN lines.

RX_EN: Enables the RX/RXN drivers on the FED Electrical Layer to transmit.

CLK_0 (FED): FED: Single-ended zero-phase-offset clock from the FED Link layer for the CLK/CLKN driver in

the FED Electrical Layer.

CLK_0 (BED): BED: Single-ended clock signal from the BED Electrical Layer to the BED Link Layer

corresponding to CLK/CLKN.

CLK_EN: Enables the CLK/CLKN drivers on the FED Electrical Layer to transmit.

CLK_DET: Indication to the BED Link layer that the BED Electrical Layer has detected a minimum active

common mode voltage on the CLK/CLKN lines.

RX_CM_DET: Indication from the BED Electrical layer to the BED Link Layer that a minimum common mode

voltage was detected on the RX/RXN lines.

RX_IN: Single-ended analog BED signal corresponding to the received differential RX/RXN signal in the BED

Electrical Layer.

TX_EN: Enables the TX/TXN drivers in the BED Electrical layer to transmit.

TX_OUT: Single-ended data to be driven differentially on TX/TXN.

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JEDEC

JEDEC Standard No. 96A.01

Page 5

3 Terminology (cont’d)

3.2 Acronyms and abbreviations (cont’d)

WLAN Wireless data packet network in a general sense, including IEEE 802.11, wireless Metropolitan

Area Networks, including IEEE 802.16; and wireless Personal Area Networks, including IEEE

802.15.

3.3 Numeric representation

The numerical values are in decimal unless indicated otherwise. The values specified in decimal are coded in natural

binary unless otherwise stated.

4 Electrical layer

The JC-61 physical data link is designed to deliver a scalable level of bandwidth and interconnect distance

performance between a Front-End IC (FED) and a Back-End IC (BED) using a robust LVDS signaling variant

similar to HyperTransport

The physical layer can operate in one of four power modes – which are distinguished by different transmission

impedance levels. The high power mode utilizes a standard differential source and load termination impedance of

100 Ω. This mode enables data links with transmission rates up to 2.3 Gb/s per data pair and up to a maximum

distance of 50 cm at full rate.

The three low-power modes utilize higher transmission impedance to save driver power. These modes utilize

nominal differential termination impedances of 200 Ω or 300 Ω, or high impedance, and are restricted for use with

shorter interconnect distances and lower rates as listed in Table 3. For the third power mode, the interface is

operated with asymmetric termination impedances utilizing a 100 Ω (differential) source impedance of the driver

together with high impedance termination at the receiver. Due to the high amount of reflection possible in this type

of line interface, only lower data rates can be supported. Power consumption is reduced in the asymmetric

termination mode for lower data rates.

It is required to use one of the termination impendence modes. An optional device impedance discovery process is

also available for switching to low power modes. At power-up the termination on the FED and BED can be decided

a priori or both the devices can power-up in the 100 Ω mode and then switch modes via register access.

4.1 Electrical layer overview

The basic I/O interface consists of three differential signals that utilize a total of 6-pins on each device. Figure 2

illustrates a typical RF-BB interface with DDR clock sourced from FED to BED. Synchronous serial NRZ data links

are provided in both directions between FED and BED. . An optional pair of pins can be assigned for a return clock

from the BED to the FED.

The RF-BB interface is distinguished from other LVDS serial interfaces by its ability to signal in either direction a

wake-up signal to a receiver side that is powered off – by using the power enable in the driver to raise the common

mode voltage level at the line receiver input. When powered off, the driver will pull down the differential

termination voltages to ground. When powered on, the driver will raise the common mode voltage of the

termination to specified levels. This capability allows the implementer of an attached device to manage the power

dissipation in the interface and system so that the total power is minimized when the interface and/or system

components are not in active use.

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