6.4GHz LMX2572低功耗射频合成器：带相同步与JESD204B支持

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LMX2572是一款高性能、低功耗的6.4 GHz宽带射频合成器，专为无线通信应用设计，特别是那些对功率效率和频率稳定性有严格要求的场合。该芯片的核心特性包括： 1. **输出频率范围**：LMX2572支持从12.5 MHz到6.4 GHz的宽广频率输出，满足多种无线通信标准的需求。 2. **低功耗**：在3.3 V供电下，该器件的功耗仅为75 mA，对于电池供电设备或电源受限的系统来说，这是一项显著的优势。 3. **卓越的相位噪声性能**：在100 kHz偏移时，其相位噪声达到惊人的-106 dBc/Hz，保证了信号的极高稳定性和信道选择性。 4. **PLL（锁相环路）特性**：具有-232 dBc/Hz的PLL Figure of Merit，表明其频率跟踪能力和锁定速度极佳，这对于频率跟踪和同步至关重要的通信系统至关重要。 5. **高精度频率分频**：内置32位的分频器，支持可编程的N-Divider，允许用户灵活设置输出频率，同时避免因整数边界效应产生的杂散干扰。 6. **相位同步功能**：除了频率合成，LMX2572还具备相位同步能力，这对于需要精确频率和相位协调的通信协议如JESD204B（高性能串行数据传输接口）非常重要。 7. **模拟前端**：包含如Charge Pump Serial Interface (CPout)、Vtune、CSB、SCK、SDI等接口，用于控制和配置芯片内部功能，以及与外部电路的通信。 8. **锁定检测器**：LockDetector提供反馈，确保系统正确锁定在期望的频率上，提高了系统的可靠性。 9. **寄存器读回**：允许用户通过特定的控制信号（如RampGenerator、FSKGenerator等）来读取和配置芯片内部状态，便于诊断和调试。 10. **时钟相关模块**：包括RampClk、RampDir、CE等，用于管理合成器的时钟操作，确保频率调整的准确性和一致性。 11. **多路复用器和分频器**：如MUXA、MUXB、Pre-R Divider、Post-R Divider等，用于信号处理的不同阶段，增强信号质量。 12. **集成LDO稳压器**：确保内部电路的电压稳定性，减少外部电源的影响。 13. **生产资料和文档**：提供了丰富的技术文档、工具软件和支持资源，方便用户理解和使用这款产品。 14. **重要注意事项**：文档结尾部分包含关于可用性、保修政策、安全关键应用使用限制、知识产权声明以及其他重要免责声明，确保用户在实际应用中了解所有相关条款。 LMX2572是一款功能强大、低功耗且具有高级相位同步特性的射频合成器，广泛应用于需要高性能无线通信的设备中。它的精密设计和丰富的功能使得它在现代通信系统中扮演着核心角色。

Pre-R

Divider

Multiplier

Post-R

Divider

OSCin

Phase

Frequency

Detector

Doubler

LMX2572

www.ti.com

SNAS740A –OCTOBER 2017–REVISED OCTOBER 2017

Product Folder Links: LMX2572

Feature Description (continued)

7.3.2 Reference Path

The reference path consists of an OSCin doubler (OSC_2X), Pre-R divider (PLL_R_PRE), Multiplier (MULT) and

a Post-R divider (PLL_R).

Figure 31. Reference Path

The Doubler allows one to double the input reference frequency up to 250 MHz, it adds minimal noise and is

useful for raising the phase detector frequency for better phase noise and also to avoid spurs. The Doubler uses

both the rising and falling edges of the input signal, so the input signal must have 50% duty cycle if the Doubler

is enabled. Note that the Multiplier cannot be used if the Doubler is engaged.

Pre-R divider is useful for reducing the input frequency so that the Multiplier can be used or to help meet the

maximum 200-MHz input frequency limitation to the Post-R divider. Otherwise, it does not have to be used.

The Multiplier multiplies frequency up, allowable multiplication are 3, 4, 5, 6, and 7. In combination with the Pre-R

and Post-R dividers, the Multiplier offers the flexibility to shift the phase detector frequency away from

frequencies that may create integer boundary spurs with the VCO and the output frequencies. Be aware that

unlike the Doubler, the Multiplier degrades the PLL figure of merit; however, this only would matter for a very

clean reference oscillator input and if the loop bandwidth was wide. The user should not use the Doubler while

using the Multiplier. The Multiplier is bypassed if its value is set to 1.

The Post-R divider can be used to further divide down the frequency to the phase detector frequency. When it is

used (PLL_R > 1), the input frequency to this divider is limited to 200 MHz.

The phase detector frequency, f

, is calculated as follows:

= f

OSCin

× OSC_2X × MULT / (PLL_R_PRE × PLL_R) (1)

Table 1 summarizes the usage boundaries of these functional blocks in the reference path.

Table 1. Reference Path Boundaries

PARAMETER VALUE

INPUT

FREQUENCY

(MHz)

OUTPUT

FREQUENCY

(MHz)

NOTES

MIN MAX MIN MAX

OSCin N/A 5 250

Doubler 0 (Bypassed), 1 (x2) 5 125 10 250

When OSC_2X = 1, Multiplier cannot be used at the same

time.

Pre-R divider 1 (Bypassed), 2, 3, …, 254, 255 5 200 0.25 200 Keep it equals 1 unless when necessary.

Multiplier 1 (Bypassed), 3, 4, 5, 6, 7 10 40 60 150

When the output frequency is greater than 100MHz, set

MULT_HI = 1.

Post-R divider 1 (Bypass), 2, 3, …, 254, 255 5 200 0.25 200

7.3.3 PLL Phase Detector and Charge Pump

The phase detector compares the outputs of the Post-R divider and N divider and generates a correction current

corresponding to the phase error until the two signals are aligned in phase. This charge-pump current is software

programmable to many different levels, allowing modification of the closed-loop bandwidth of the PLL.

SYSREF

VCO

RFoutA

÷2,4,8,16,

32,64,128,

256

MUX BMUX A

RFoutB

LMX2572

SNAS740A –OCTOBER 2017–REVISED OCTOBER 2017

www.ti.com

Product Folder Links: LMX2572

7.3.4 PLL N Divider and Fractional Circuitry

The N divider includes fractional compensation and can achieve any fractional denominator (PLL_DEN) from 1 to

– 1). The integer portion of N (PLL_N) is the whole part of the N divider value, and the fractional portion,

frac

= PLL_NUM / PLL_DEN, is the remaining fraction. PLL_N, PLL_NUM and PLL_DEN are software

programmable. The higher the denominator, the finer the resolution step of the output. For example, even when

using f

= 200 MHz, the output can increment in steps of 200 MHz / (2

– 1) = 0.0466 Hz. Equation 2 shows

the relationship between the phase detector and VCO frequencies. Note that in SYNC mode, there is an extra

divider that is not shown in Equation 2.

VCO

= f

× [PLL_N + (PLL_NUM / PLL_DEN)] (2)

The multi-stage noise-shaping (MASH) sigma-delta modulator that controls the fractional division is also

programmable from integer mode to fourth order, all of these settings work for integer channel where PLL_NUM

= 0. To make the fractional spurs consistent, the modulator is reset any time that the R0 register is programmed.

The N divider has minimum value restrictions based on the modulator order. Furthermore, the PFD_DLY_SEL bit

must be programmed in accordance to Table 2.

Table 2. Minimum N Divider Restrictions

VCO

FREQUENCY

(GHz)

MASH ORDER

INTEGER FIRST ORDER SECOND ORDER THIRD ORDER FOURTH ORDER

N PFD_DLY_SEL N PFD_DLY_SEL N PFD_DLY_SEL N PFD_DLY_SEL N PFD_DLY_SEL

VCO

< 4 20 0 25 1 26 1 32 2 44 4

4 ≤ f

VCO

< 4.9 24 1 29 2 30 2 32 2 44 4

4.9 ≤ f

VCO

≤ 6.4 24 1 29 2 30 2 36 3 48 5

7.3.5 Voltage Controlled Oscillator

The LMX2572 includes a fully integrated VCO. The VCO generates a frequency which varies with the tuning

voltage from the loop filter. The entire VCO frequency range, 3.2 to 6.4 GHz, covers an octave that allows the

channel divider to take care of frequencies below the lower bound.

In order to reduce the VCO tuning gain, thus improving the VCO phase noise performance, the VCO frequency

range is divided into 6 different frequency bands. This creates the need for frequency calibration in order to

determine the correct frequency band given a desired output frequency. The VCO is also calibrated for amplitude

to optimize phase noise. These calibration routines are activated any time that the R0 register is programmed

with the FCAL_EN bit equals one. It is important that a valid OSCin signal must present before VCO calibration

begins. This device will support a full sweep of the valid temperature range of 125 °C (–40 °C to 85 °C) without

having to re-calibrate the VCO. This is important for continuous operation of the synthesizer under the most

extreme temperature variation.

7.3.6 Channel Divider

To go below the VCO lower bound of 3.2 GHz, the channel divider can be used. The channel divider consists of

several segments, and the total division value is equal to the multiplication of them. Therefore, not all values are

valid.

Figure 32. Channel Divider

The channel divider is automatically powered up whenever the MUXs have selected divided down output or

SYSREF output, regardless of whether the RF output buffers are turned on or not. When an output is not used,

TI recommends selecting the VCO output (OUTx_MUX = 1) to ensure that the channel divider is not

unnecessarily powered up.

Device 1

Device 2

OUT

OSCin

SYNC

OSCin

OUT

LMX2572

www.ti.com

SNAS740A –OCTOBER 2017–REVISED OCTOBER 2017

Product Folder Links: LMX2572

Table 3. Channel Divider

OUTA_MUX OUTB_MUX CHANNEL DIVIDER

0: Channel divider output Don't care

Powered up

Don't care

0: Channel divider output

2: SYSREF output

All other cases Powered down

7.3.7 Output Buffer

The output buffers are differential push-pull type buffer, therefore, no external pull-up to V

is required. The

output impedance of the buffer is very small, as such, the buffer can be AC-coupled to drive a 50-Ω load. Output

power of the buffer can be programed to various levels. The buffer can be disabled while still keeping the PLL in

lock. Buffer A supports direct VCO output or divided down output. Buffer B supports direct VCO output, divided

down output or SYSREF output.

7.3.8 Lock Detect

The MUXout pin can be configured to output a signal that gives an indication for the PLL being locked. If the

MUXout pin is configured as lock detect output (MUXOUT_LD_SEL = 1), when the device is locked, the MUXout

pin output is a logic HIGH voltage. When the device is unlocked, MUXout pin output is a logic LOW voltage.

There are options to select the definition of PLL being locked. If LD_TYPE = 0, lock detect asserts a HIGH output

after the VCO has finished calibration and the LD_DLY timeout counter is finished. If LD_TYPE = 1, in addition to

the VCO calibration and counter check, lock detect will assert a HIGH output if the VCO tuning voltage is also

within an acceptable limits.

7.3.9 Register Readback

The MUXout pin can also be configured for to read back useful information from the device. Common uses for

readback are:

• Read back registers to ensure that they have been programmed to the correct value. LMX2572 allows any of

its registers to be read back.

• Read back the lock detect status to determine if the PLL is in lock.

• Read back VCO calibration information so that it can be used to improve the lock time.

7.3.10 Powerdown

The LMX2572 can be powered up and down using the CE pin or the POWERDOWN bit. All registers are

preserved in memory while it is powered down. When the device comes out of the powered down state, either by

resuming the POWERDOWN bit to zero or by pulling back CE pin HIGH (if it was powered down by CE pin), it is

required that register R0 with FCAL_EN = 1 be programmed again to re-calibrate the device.

7.3.11 Phase Synchronization

The SYNC pin allows one to synchronize the LMX2572 such that the delay from the rising edge of th OSCin

signal to the RF output signal is deterministic. Phase synchronization is especially useful if there are multiple

LMX2572 devices in a system while it is desirable to have all the RF outputs aligned in phase.

Figure 33. Phase Synchronization

Time

Output frequency

Time

Output frequency

Manual Ramping Mode Automatic Ramping Mode

LMX2572

SNAS740A –OCTOBER 2017–REVISED OCTOBER 2017

www.ti.com

Product Folder Links: LMX2572

Initially, the devices are locked to the input, but are not synchronized. The user sends a synchronization pulse

that is re-clocked to the next rising edge of the OSCin pulse. After a given time, t

, the devices are synchronized.

This time is dominated by the sum of the VCO calibration time, the analog settling time of the PLL loop, and the

MASH_RST_COUNT, if used in fractional mode. After synchronization, both devices will have a deterministic

delay of t

, related to OSCin.

7.3.12 Phase Adjustment

The LMX2572 can use the sigma-delta modulator to adjust the output signal phase with respect to the input

reference. The phase shift every time you write the value of MASH_SEED is:

Phase shift in degree = 360° x (MASH_SEED / PLL_DEN) x (P / CHDIV) (3)

where P = 2 when VCO_PHASE_SYNC_EN = 1, else P = 1

For example, if

• MASH_SEED = 800

• PLL_DEN = 1000

• CHDIV = 32

• VCO_PHASE_SYNC_EN = 0

Phase shift = 360° x (800 / 1000) x (1 / 32) = 9°. If we write 800 to MASH_SEED 40 times, then we will shift the

phase by 360°.

There are a couple of restrictions when using phase adjustment:

• Phase adjustment does not work with MASH_ORDER equals 0 (Integer mode) or 1 (First order).

• Phase adjustment is possible with integer channels (PLL_NUM = 0) as long as MASH_ORDER is greater

than 1.

• PLL_DEN must be greater than PLL_NUM + MASH_SEED.

7.3.13 Ramping Function

The LMX2572 supports the ability to make frequency ramping waveforms using manual mode or automatic

mode.

In manual ramping mode, the user defines a step and uses the RampClk and RampDir pins to create the ramp.

The output frequency jumps from one frequency to another frequency on each ramp.

In automatic ramping mode, the user sets up the ramp with up to two linear segments in advance and the device

automatically creates this ramp. The output waveform is a continuous frequency sweep between the start and

end frequencies. If the frequency ramping range is small, approximately 10 MHz, no VCO calibration break is

needed in the middle of the ramp.

When using ramp, the followings need to be set accordingly:

• Phase detector frequency must be between f

OSCin

/ 2

CAL_CLK_DIV

and 125 MHz.

• OUT_FORCE = 1 to force the RF outputs not to be automatically muted during VCO calibration.

• LD_DLY = 0 to avoid interfering with VCO calibration.

• PLL_DEN = 2

– 1. The actual denominator value being used in ramping mode is 2

Figure 34. Ramping Modes

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