SystemVerilog3.1扩展：硬件描述语言助力架构建模与验证

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"SystemVerilog3.1 Accellera’s Extensions to Verilog®" SystemVerilog是一种高级硬件描述语言，它是Verilog的扩展版本，旨在增强和丰富Verilog的功能，特别是在创建和验证抽象架构级别的模型方面。这个资料是Accellera组织发布的SystemVerilog3.1版本，该组织在2002年和2003年对其进行了开发和更新。SystemVerilog的扩展内容主要针对IEEE1364-2001标准的Verilog语言，目的是为了提高设计和验证的效率与精确度。 SystemVerilog的关键扩展包括： 1. **面向对象编程（OOP）**：SystemVerilog引入了类、接口、包等概念，使得设计者可以使用类似于软件工程中的面向对象编程技术来组织和管理设计模块，提高了代码复用性和可维护性。 2. **高级数据类型**：除了传统的位矢量类型，SystemVerilog还提供了数组、结构体、联合体、枚举和位操作等更丰富的数据类型，便于描述复杂的数据结构。 3. **并行处理**：SystemVerilog支持任务和函数，它们可以在不同的线程中并行执行，增强了并发性和时序控制。 4. **断言和覆盖**：SystemVerilog提供了强大的断言机制，用于在设计中插入静态和动态的错误检查，以及覆盖分析，帮助验证工程师更好地理解设计的行为。 5. **接口**：接口是一种定义通信协议的独立实体，可以包含方法和信号，方便模块间的连接和交互。 6. **非阻塞赋值**：非阻塞赋值（<=）允许异步信号的处理，避免了不必要的同步问题，提高了仿真性能。 7. **随机化**：SystemVerilog的随机化功能允许自动生成测试向量，简化了测试平台的构建，增强了测试覆盖率。 8. **约束**：通过使用约束，可以指定变量的取值范围或条件，进一步指导随机化过程。 9. **门控时钟**：SystemVerilog支持门控时钟，能够更准确地模拟时钟域交叉的场景，减少时序分析的复杂性。 10. **封装和继承**：这些OOP特性允许设计者定义新的类，基于现有的类进行扩展，实现设计的模块化。 11. **异常处理**：SystemVerilog引入了异常处理机制，允许在设计中处理意外情况。 12. **系统任务和函数**：SystemVerilog提供了一系列内置的系统任务和函数，如$display、$finish、$stop等，方便调试和日志记录。 SystemVerilog通过增加这些高级特性，极大地提升了硬件设计和验证的灵活性和效率，使其成为现代SoC（System on Chip）设计中不可或缺的语言工具。在实际应用中，SystemVerilog不仅适用于设计，也广泛应用于验证，为整个半导体行业的设计流程带来了革命性的变化。

Accellera

SystemVerilog 3.1 Extensions to Verilog-2001

SystemVerilog adds the ability to specify unsized literal single bit values with a preceding apostrophe (

’ ), but

without the base specifier. All bits of the unsized value are set to the value of the specified bit. In a self-deter-

mined context these literals have a width of 1 bit, and the value is treated as unsigned.

’0, ’1, ’X, ’x, ’Z, ’z // sets all bits to this value

2.4 Real literals

The default type is real for fixed point format (e.g. 1.2), and exponent format (e.g. 2.0e10).

A cast can be used to convert literal

real values to the shortreal type (e.g., shortreal’(1.2) ). Casting

is described in Section 3.14.

2.5 Time literals

Time is written in integer or fixed point format, followed without a space by a time unit (fs ps ns us ms s

step

). For example:

0.1ns

40ps

The time literal is interpreted as a realtime value scaled to the current time unit and rounded to the current

time precision. Note that if a time literal is used as an actual parameter to a module or interface instance, the

current time unit and precision are those of the module or interface instance.

2.6 String literals

A string literal is enclosed in quotes and has its own data type. Non-printing and other special characters are

preceded with a backslash. SystemVerilog adds the following special string characters:

\v vertical tab

\f form feed

\a bell

\x02 hex number

A string literal must be contained in a single line unless the new line is immediately preceded by a

\ (back

slash). In this case, the back slash and the new line are ignored. There is no predefined limit to the length of a

string literal.

A string literal can be assigned to a character, or a packed array, as in Verilog-2001. If the size differs, it is right

justified.

byte c1 = "A" ; bit [7:0] d = "\n" ;

bit [0:11] [7:0] c2 = "hello world\n" ;

A string literal can be assigned to an unpacked array of characters, and a zero termination is added like in C. If

the size differs, it is left justified.

byte c3 [0:12] = "hello world\n" ;

Packed and unpacked arrays are discussed in Section 4. The difference between string literals and array literals

is discussed in Section 2.7, which follows.

String literals can also be cast to a packed or unpacked array, which shall follow the same rules as assigning a

literal string to a packed or unpacked array. Casting is discussed in Section 3.14.

SystemVerilog 3.1 also includes a

string data type to which a string literal can be assigned. Variables of type

Accellera

SystemVerilog 3.1 Extensions to Verilog-2001

Section 3

Data Types

3.1 Introduction (informative)

To provide for clear translation to and from C, SystemVerilog supports the C built-in types, with the meaning

given by the implementation C compiler. However, to avoid the duplication of

int and long without causing

confusion, in SystemVerilog,

int is 32 bits and longint is 64 bits. The C float type is called shortreal in

SystemVerilog, so that it is not be confused with the Verilog-2001

real type.

Verilog-2001 has net data types, which can have 0, 1, X or Z, plus 7 strengths, giving 120 values. It also has

variable data types such as

reg, which have 4 values 0, 1, X, Z. These are not just different data types, they are

used differently. SystemVerilog adds another 4-value data type, called

logic (see Sections 3.3.2 and 5.6).

SystemVerilog 3.1 adds string,

chandle and class data types, and enhances the Verilog event and System-

Verilog 3.0

enum data types. SystemVerilog 3.1 also extends the user defined types by providing support for

object-oriented class.

Verilog-2001 provides arbitrary fixed length arithmetic using

reg data types. The reg type can have bits at X

or Z, however, and so are less efficient than an array of bits, because the operator evaluation must check for X

and Z, and twice as much data must be stored. SystemVerilog adds a

bit type which can only have bits with 0

or 1 values. See Section 3.3.2 on 2-state data types.

Automatic type conversions from a smaller number of bits to a larger number of bits involve zero extensions if

unsigned or sign extensions if signed, and do not cause warning messages. Automatic truncation from a larger

number of bits to a smaller number does cause a warning message. Automatic conversions between

logic and

bit do not cause warning messages. To convert a logic value to a bit, 1 converts to 1, anything else to 0.

User defined types are introduced by

typedef and must be defined before they are used. Data types can also

be parameters to modules or interfaces, making them like class templates in object-oriented programming. One

routine can be written to reverse the order of elements in any array, which is impossible in C and in Verilog.

Structures and unions are complicated in C, because the tags have a separate name space. SystemVerilog fol-

lows the C syntax, but without the optional structure tags.

See also Section 4 on arrays.

Accellera

Extensions to Verilog-2001 SystemVerilog 3.1

3.2 Data type syntax

Syntax 3-1—data types (excerpt from Annex A)

3.3 Integer data types

SystemVerilog offers several integer data types, representing a hybrid of both Verilog and C data types:

Table 3-1: Integer data types

shortint 2-state SystemVerilog data type, 16 bit signed integer

int 2-state SystemVerilog data type, 32 bit signed integer

longint 2-state SystemVerilog data type, 64 bit signed integer

byte 2-state SystemVerilog data type, 8 bit signed integer or ASCII character

bit 2-state SystemVerilog data type, user-defined vector size

data_type ::=

integer_vector_type [ signing ] { packed_dimension } [ range ]

| integer_atom_type [ signing ]

| type_declaration_identifier { packed_dimension }

| non_integer_type

| struct packed [ signing ] { { struct_union_member } } { packed_dimension }

| union packed [ signing ] { { struct_union_member } } { packed_dimension }

| struct [ signing ] { { struct_union_member } }

| union [ signing ] { { struct_union_member } }

| enum [ integer_type [ signing ] { packed_dimension } ]

{ enum_identifier [ = constant_expression ] { , enum_identifier [ = constant_expression ] } }

| string

| event

| chandle

| class_scope_type_identifier

class_scope_type_identifier::=

class_identifier :: { class_identifier :: } type_declaration_identifier

| class_identifier :: { class_identifier :: } class_identifier

integer_type ::= integer_vector_type | integer_atom_type

integer_atom_type ::= byte | shortint | int | longint | integer

integer_vector_type ::= bit | logic | reg

non_integer_type ::= time | shortreal | real | realtime

signing ::= signed | unsigned

simple_type ::= integer_type | non_integer_type | type_identifier

struct_union_member ::= { attribute_instance } data_type

list_of_variable_identifiers_or_assignments ;

variable_decl_assignment ::=

variable_identifier [ variable_dimension ] [ = constant_expression ]

| variable_identifier [ ] = new [ constant_expression ] [ ( variable_identifier ) ]

| class_identifier [ parameter_value_assignment ] = new [ ( list_of_arguments ) ]

// from Annex A.2.2.1

// from Annex A.2.4

Accellera

SystemVerilog 3.1 Extensions to Verilog-2001

3.3.1 Integral types

The term integral is used throughout this document to refer to the data types that can represent a single basic

integer data type,

packed array, packed struct, packed union, enum, or time.

3.3.2 2-state (two-value) and 4-state (four-value) data types

Types that can have unknown and high-impedance values are called 4-state types. These are

logic, reg,

integer and time. The other types do not have unknown values and are called 2-state types, for example bit

and int.

The difference between

int and integer is that int is 2-state logic and integer is 4-state logic. 4-state val-

ues have additional bits that encode the X and Z states. 2-state data types can simulate faster, take less memory,

and are preferred in some design styles.

3.3.3 Signed and unsigned data types

Integer types use integer arithmetic and can be signed or unsigned. This affects the meaning of certain opera-

tors such as ‘<’, etc.

int unsigned ui;

int signed si;

The data types byte, shortint, int, integer and longint default to signed. The data types bit, reg

and logic default to unsigned, as do arrays of these types.

Note that the

signed keyword is part of Verilog-2001. The unsigned keyword is a reserved keyword in Ver-

ilog-2001, but is not utilized.

See also Section 7, on operators and expressions.

3.4 Real and shortreal data types

The real

data type is from Verilog-2001, and is the same as a C double. The shortreal data type is a Sys-

temVerilog data type, and is the same as a C

float.

3.5 Void data type

The void data type represents non-existent data. This type can be specified as the return type of functions,

indicating no return value.

3.6 chandle data type

The chandle data type represents storage for pointers passed using the DPI Direct Programming Interface

logic 4-state SystemVerilog data type, user-defined vector size with different use rules from reg

reg 4-state Verilog-2001 data type, user-defined vector size

integer 4-state Verilog-2001 data type, at least 32 bit signed integer

time 4-state Verilog-2001 data type, 64-bit integer

The real and shortreal types are represented as described by IEEE 734-1985, an IEEE standard for floating point numbers.

Table 3-1: Integer data types

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