5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MEM_MB_ADD1
M_B_DQ42
M_B_DQ41
M_B_DQ40
M_B_DQ43
M_B_DQ14
M_B_DQ13
M_B_DQ12
M_B_DQ15
M_B_DM4
M_B_DQS3
M_B_DQ0
MEM_MB_ADD2
M_B_DQ46
M_B_DQ45
M_B_DQ44
M_B_DQ47
M_B_DQ19
M_B_DQ18
M_B_DQ17
M_B_DQ16
M_B_DQS4
M_B_DM5
MEM_MB_ADD3
M_B_DQ51
M_B_DQ50
M_B_DQ49
M_B_DQ48
M_B_DQ23
M_B_DQ22
M_B_DQ21
M_B_DQ20
M_B_DQ1
M_B_DM0
MEM_MB_ADD4
M_B_DQS5
M_B_DM6
M_B_DQ53
M_B_DQ52
M_B_DQ24
M_B_DQ55
M_B_DQ54
M_B_DQ27
M_B_DQ26
M_B_DQ25
M_B_DQ2
MEM_MB_ADD5
M_B_DM1
M_B_DM7
M_B_DQS6
M_B_DQ57
M_B_DQ56
M_B_DQS0
M_B_DQ59
M_B_DQ58
M_B_DQ31
M_B_DQ30
M_B_DQ29
M_B_DQ28
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
M_B_DQ3
M_B_DM2
M_B_DQS7
M_B_DQ63
M_B_DQ62
M_B_DQ61
M_B_DQ60
M_B_DQ33
M_B_DQ32
M_B_DQ35
M_B_DQ34
M_B_DQS1
MEM_MB_ADD12
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
M_B_DQ5
M_B_DQ4
M_B_DQ7
M_B_DQ6
MEM_MB_ADD0
M_B_DQ39
M_B_DQ38
M_B_DQ37
M_B_DQ36
M_B_DM3
M_B_DQ8
M_B_DQ11
M_B_DQ10
M_B_DQ9
M_B_DQS2
SB_SMBCLK
SB_SMBDATA
PM_EXTTS#1
PM_EXTTS#1
+3.3V_RUN
+1.5V_SUS
+3.3V_RUN
+0.75V_DDR_VTT
+1.5V_SUS
+1.5V_SUS
+V_DD R_REF
MEM_MB_W E# (9)
MEM_MB0_CS#0 (9)
DDR 3_B_DRAMRST#(9)
MEM_MB_CAS# (9)
MEM_MB0_ODT0(9)
MEM_MB0_ODT1(9)
MEM_MB_CKE0 (9)
MEM_MB_CKE1 (9)
MEM_MB0_CS#1 (9)
MEM_MB_CLK0_P (9)
MEM_MB_CLK0_N (9)
MEM_MB_CLK1_P (9)
MEM_MB_CLK1_N (9)
MEM_MB_BANK0(9)
MEM_MB_BANK2(9)
MEM_MB_BANK1(9)
MEM_MB_RAS# (9)
M_B_DQ[63..0](9)
SB_SMBCLK (18,76)
SB_SMBDATA (18,76)
MEM_MB_ADD[0..15](9)
M_B_DM[7..0] (9)
M_B_DQS#0(9)
M_B_DQS#2(9)
M_B_DQS#1(9)
M_B_DQS#3(9)
M_B_DQS#4(9)
M_B_DQS#5(9)
M_B_DQS#6(9)
M_B_DQS#7(9)
M_B_DQS0(9)
M_B_DQS1(9)
M_B_DQS2(9)
M_B_DQS3(9)
M_B_DQS4(9)
M_B_DQS5(9)
M_B_DQS6(9)
M_B_DQS7(9)
Title
Size Docum ent Number Rev
Date: Sheet
of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., H sichih,
Taipei Hsien 221, Taiwan, R.O.C.
Berry AMD Discrete/UMA
A00
DDR3-SODIMM2
19 95Thursday, March 04, 2010
<Core Design>
Title
Size Docum ent Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., H sichih,
Taipei Hsien 221, Taiwan, R.O.C.
Berry AMD Discrete/UMA
A00
DDR3-SODIMM2
19 95Thursday, March 04, 2010
<Core Design>
Title
Size Docum ent Number Rev
Date: Sheet of
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., H sichih,
Taipei Hsien 221, Taiwan, R.O.C.
Berry AMD Discrete/UMA
A00
DDR3-SODIMM2
19 95Thursday, March 04, 2010
<Core Design>
Note:
SA0 = 0, SA1 = 1
SO-DIMMB SPD Address is 0xA4
SO-DIMMB TS Address is 0x34
SO-DIMMB is placed farther from
the Processor than SO-DIMMA
Place these caps
close to VTT1 and
VTT2.
SODIMM B DECOUPLING (ONE CAP PER POWER PIN)
Layout Note:
Place these Caps near
SO-DIMMB.
H = 9.2mm
SSID = MEMORY
3.3V, 2mA
1.5V, 3.5A
0.75V, 0.5A
9/14 9/23
9/23
9/23
9/23
10/7
11/10
1231-2
0108-3
12
C1902
SCD1U10V2KX-5GP
C1902
SCD1U10V2KX-5GP
12
C1920
SCD1U10V2KX-5GP
DY
C1920
SCD1U10V2KX-5GP
DY
12
C1918
SC2D2U6D3V3KX-GP
C1918
SC2D2U6D3V3KX-GP
12
C1907
SCD1U10V2KX-5GP
C1907
SCD1U10V2KX-5GP
12
C1915
SC10U10V5ZY-1GP
DY
C1915
SC10U10V5ZY-1GP
DY
12
C1909
SCD1U10V2KX-5GP
C1909
SCD1U10V2KX-5GP
12
C1910
SCD1U10V2KX-5GP
C1910
SCD1U10V2KX-5GP
1 2
R19064K7R2J-2-GP
DY
R19064K7R2J-2-GP
DY
12
C1905
SCD1U10V2KX-5GP
C1905
SCD1U10V2KX-5GP
12
C1912
SC10U10V5ZY-1GP
DY
C1912
SC10U10V5ZY-1GP
DY
12
C1911
SCD1U10V2KX-5GP
C1911
SCD1U10V2KX-5GP
12
C1906
SCD1U10V2KX-5GP
C1906
SCD1U10V2KX-5GP
12
C1921
SCD1U10V2KX-5GP
DY
C1921
SCD1U10V2KX-5GP
DY
12
C1908
SCD1U10V2KX-5GP
C1908
SCD1U10V2KX-5GP
12
C1922
SCD1U10V2KX-5GP
C1922
SCD1U10V2KX-5GP
12
C1917
SC10U10V5ZY-1GP
DY
C1917
SC10U10V5ZY-1GP
DY
12
C1919
SCD1U10V2KX-5GP
DY
C1919
SCD1U10V2KX-5GP
DY
12
C1904
SCD01U50V3KX-4GP
C1904
SCD01U50V3KX-4GP
12
C1914
SC10U10V5ZY-1GP
DY
C1914
SC10U10V5ZY-1GP
DY
12
C1913
SC10U10V5ZY-1GP
DY
C1913
SC10U10V5ZY-1GP
DY
12
C1916
SC10U10V5ZY-1GP
DY
C1916
SC10U10V5ZY-1GP
DY
A0
98
A1
97
A2
96
A3
95
A4
92
A5
91
A6
90
A7
86
A8
89
A9
85
A10/AP
107
A11
84
A12
83
A13
119
A14
80
A15
78
A16/BA2
79
BA0
109
BA1
108
DQ0
5
DQ1
7
DQ2
15
DQ3
17
DQ4
4
DQ5
6
DQ6
16
DQ7
18
DQ8
21
DQ9
23
DQ10
33
DQ11
35
DQ12
22
DQ13
24
DQ14
34
DQ15
36
DQ16
39
DQ17
41
DQ18
51
DQ19
53
DQ20
40
DQ21
42
DQ22
50
DQ23
52
DQ24
57
DQ25
59
DQ26
67
DQ27
69
DQ28
56
DQ29
58
DQ30
68
DQ31
70
DQ32
129
DQ33
131
DQ34
141
DQ35
143
DQ36
130
DQ37
132
DQ38
140
DQ39
142
DQ40
147
DQ41
149
DQ42
157
DQ43
159
DQ44
146
DQ45
148
DQ46
158
DQ47
160
DQ48
163
DQ49
165
DQ50
175
DQ51
177
DQ52
164
DQ53
166
DQ54
174
DQ55
176
DQ56
181
DQ57
183
DQ58
191
DQ59
193
DQ60
180
DQ61
182
DQ62
192
DQ63
194
DQS0#
10
DQS1#
27
DQS2#
45
DQS3#
62
DQS4#
135
DQS5#
152
DQS6#
169
DQS7#
186
DQS0
12
DQS1
29
DQS2
47
DQS3
64
DQS4
137
DQS5
154
DQS6
171
DQS7
188
ODT0
116
ODT1
120
VREF_DQ
1
VSS
2
NP1
NP1
NP2
NP2
RAS#
110
WE#
113
CAS#
115
CS0#
114
CS1#
121
CKE0
73
CKE1
74
CK0
101
CK0#
103
CK1
102
CK1#
104
DM0
11
DM1
28
DM2
46
DM3
63
DM4
136
DM5
153
DM6
170
DM7
187
SDA
200
SCL
202
VDDSPD
199
SA0
197
SA1
201
VREF_CA
126
VDD18
124
NC#1
77
NC#2
122
NC#/TEST
125
VDD3
81
VDD4
82
VDD5
87
VDD6
88
VDD7
93
VDD8
94
VDD9
99
VDD10
100
VDD13
111
VDD14
112
VDD15
117
VDD16
118
VSS
3
VSS
8
VSS
9
VSS
13
VSS
14
VSS
19
VSS
20
VSS
25
VSS
26
VSS
31
VSS
32
VSS
37
VSS
38
VSS
43
VSS
44
VSS
48
VSS
49
VSS
54
VSS
55
VSS
60
VSS
61
VDD1
75
VSS
65
VSS
66
VSS
71
VSS
72
VDD2
76
VDD11
105
VDD12
106
VDD17
123
VSS
127
VSS
128
VSS
134
VSS
133
VSS
138
VSS
139
VSS
144
VSS
145
VSS
151
VSS
150
VSS
155
VSS
156
VSS
161
VSS
162
VSS
167
VSS
168
VSS
173
VSS
172
VSS
179
VSS
178
VSS
185
VSS
184
VSS
189
VSS
190
VSS
195
VSS
196
RESET#
30
EVENT#
198
VSS
205
VSS
206
VTT1
203
VTT2
204
DM2
DDR 3-204P-40-GP-U
DM2
DDR 3-204P-40-GP-U