贝叶斯模型融合：模拟与混合信号电路的多元矩估计新方法

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"通过贝叶斯模型融合对模拟和混合信号电路进行有效的多元矩估计" 在电子工程领域，尤其是在模拟和混合信号电路的设计与验证中，参数的产出率估算是一项至关重要的任务，但却极具挑战性。这涉及到在硅片前或硅片后的验证阶段对电路性能的评估。本文提出了一种新颖的贝叶斯模型融合方法，用于高效地估计多个相关性能指标的多变量矩。这种方法充分利用了早期阶段的先验知识，从而提高了估计的准确性和效率。在传统的电路验证中，由于电路性能通常由多个相互关联的参数决定，因此对这些参数的统计特性进行建模和分析至关重要。论文的核心思想是将多个性能指标视为联合高斯分布，这种建模方式能够有效地捕捉到参数间的依赖关系。同时，利用共轭先验理论，将前期的先验知识编码为一个正态-Wishart分布。Wishart分布常用于作为多元正态分布的逆维纳滤波器，它能提供对协方差结构的灵活建模。贝叶斯推理在此扮演关键角色，它允许利用现有的先验信息来更新我们的知识，随着新数据（即后期阶段的少量样本）的引入，可以准确地估计多变量矩。这一方法的优点在于，即使在后期阶段样本量有限的情况下，也能提供精确的估计结果，显著降低了对大量实验数据的依赖，从而降低了时间和成本。论文通过多个电路实例验证了所提方法的有效性，证明了在模拟和混合信号电路的性能评估中，贝叶斯模型融合策略能显著提高参数产出率的估计精度。这种方法不仅适用于预硅验证，也可应用于后硅调试阶段，对于优化电路设计、提升整体系统性能以及降低制造风险具有重要意义。这项工作展示了如何通过创新的贝叶斯方法，结合先验知识，实现对复杂模拟和混合信号电路的高效多变量矩估计，为电路验证提供了一种强大而实用的工具。这为未来的电路设计和优化提供了新的研究方向，特别是在面对日益复杂的电路系统和不断提高的性能要求时，这样的方法显得尤为必要。

Efficient Multivariate Moment Estimation via Bayesian Model

Fusion for Analog and Mixed-Signal Circuits

Qicheng Huang

, Chenlei Fang

, Fan Yang

1,*

, Xuan Zeng

1,*

and Xin Li

1,2

State Key Lab of ASIC & System, Microelectronics Department, Fudan University, Shanghai, P. R. China

Electrical & Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, USA

ABSTRACT

A critical-yet-challenging problem of analog/mixed-signal circuit

validation in either pre-silicon or post-silicon stage is to estimate

the parametric yield of the performances. In this paper, we

propose a novel Bayesian model fusion method for efficient

multivariate moment estimation of multiple correlated

performance metrics by borrowing the prior knowledge from the

early stage. The key idea is to model the multiple performance

metrics as a jointly Gaussian distribution and encode the prior

knowledge as a normal-Wishart distribution according to the

theory of conjugate prior. The late-stage multivariate moments

can be accurately estimated by Bayesian inference with very few

late-stage samples. Several circuit examples demonstrate that the

proposed method can achieve up to 16× cost reduction over the

traditional method without surrendering any accuracy.

1. INTRODUCTION

The continuous scaling of integrated circuits (ICs) leads to

severe process variations. Process variations, in terms of doping

profiles, interconnect widths, channel lengths, etc., lead to large-

scale variations in the corresponding electrical parameters (e.g.,

resistance, capacitance, threshold voltage, etc.) of CMOS

transistors and metal interconnects. These variations would

consequently impact the parametric yield of analog and mixed-

signal (AMS) circuits. Hence, accurate yield estimation is one of

the critical tasks for both pre-silicon verification and post-silicon

validation of AMS circuits in order to improve the circuit

performance and/or reduce the manufacturing cost at advanced

technology nodes [1-4].

Recently, post-silicon tuning and self-healing techniques have

been proposed to address the yield loss posed by process

variations. These methods adaptively adjust a number of tunable

knobs (e.g., bias current) to meet the performance requirement

after manufacturing [3-4]. They pose great challenges to yield

estimation, as a large number of samples must be collected for a

highly complex, tunable circuit by either circuit simulation (for

pre-silicon verification) or silicon measurement (for post-silicon

validation). Both circuit simulation and silicon measurement are

time-consuming. For example, one single post-layout simulation

of a large-scale AMS circuit such as PLL or SRAM could take

several days to finish. On the other hand, due to the time-to-

market pressure, only a small number of silicon measurements can

be taken at the post-silicon validation stage, especially because the

measurements of a number of AMS performance metrics such as

bit rate error are extremely time-consuming. Hence, it is

impossible to collect a large number of samples for yield

estimation for either pre-silicon verification or post-silicon

validation.

To address this issue, Bayesian Model Fusion (BMF) has been

proposed to accurately estimate the parametric yield and/or the

statistical distribution of circuit performance for both pre-silicon

verification and post-silicon validation [5-8]. The key idea of

BMF is to borrow the knowledge of an early stage (e.g., pre-

layout simulation) to accurately estimate the yield and/or

distribution at the late stage (e.g., post-layout simulation) with

very few late-stage samples. Because the simulation and/or

measurement data from the early and late stages are derived from

the same circuit, they are expected to be highly correlated. By

fusing the early-stage and late-stage data, the parametric yield

and/or performance distribution of the late stage can be accurately

estimated with few samples and, hence, low computational and/or

measurement cost.

The BMF method was previously developed for moment

estimation of AMS circuits where only a single performance

metric is considered [5-8]. However, the parametric yield value of

an AMS circuit is often defined by multiple correlated

performance metrics. Motivated by this observation, we propose a

novel multivariate moment estimation method in this paper.

Particularly, we assume that the probability distribution of

multiple AMS performance metrics is jointly (or, multivariate)

Gaussian and our objective is to accurately estimate its means

vector and covariance matrix.

Towards this goal, we borrow the early-stage data and encode

the prior knowledge as a normal-Wishart distribution according to

the conjugate prior theory from the statistics community [14].

Next, the prior knowledge is combined with very few late-stage

data via Bayesian inference to accurately estimate the mean vector

and covariance matrix for multiple AMS performance metrics. As

will be demonstrated by our experimental results in Section 5, the

proposed method can achieve up to 16× cost reduction over the

traditional Maximum Likelihood Estimation (MLE) method

without surrendering any accuracy.

It is important to note that the probability distribution of AMS

performance metrics may not be accurately modeled as a jointly

Gaussian distribution [9-13]. However, accurately estimating a

non-Gaussian distribution often needs to collect a large number of

samples and, hence, is not feasible with limited data. Since we

focus on the problem of pre-silicon verification and post-silicon

validation with an extremely small data set, we constrain our

discussions to Gaussian distribution in this paper. How to extend

the proposed BMF method to other non-Gaussian distributions

will be further studied in our future researches (e.g., by estimating

and matching the high-order moments).

The reminder of this paper is organized as follows. In Section

* Corresponding authors: {yangfan, xzeng}@fudan.edu.cn.

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Abstracting with credit is permitted. To copy otherwise, or republish, t

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DAC '15, June 07 - 11, 2015, San Francisco, CA, USA

http://dx.doi.org/10.1145/2744769.2744832

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贝叶斯模型融合：模拟与混合信号电路的多元矩估计新方法

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