AT91SAM9G45 ARM9处理器datasheet：高性能与多功能接口

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AT91SAM9G45是一款由Atmel公司基于ARM926EJ-S内核设计的高性能微控制器，旨在提供强大的用户界面功能和高速数据连接能力。这款处理器特别适合需要高效率和多样接口的应用场景，例如LCD控制、电阻式触摸屏、摄像头接口、音频处理、以太网（10/100Mbps）以及USB和SDIO高速通信。该芯片的核心特性包括400MHz运行频率，能够支持多条100+Mbps的数据线，确保了与网络或本地存储设备的高效交互，从而为用户提供流畅的体验。AT91SAM9G45集成了多种存储解决方案，如DDR2内存接口和NAND闪存，用于程序和数据存储。内部的133MHz多层总线架构配合37个DMA通道，以及双外部总线接口和分布式内存（包括64KB的SRAM，可以配置为紧密耦合内存TCM），这些设计共同支撑了处理器和高速外围设备所需的高带宽需求。此外，AT91SAM9G45的I/O接口兼容1.8V和3.3V工作电压，这使得内存接口和外围设备的供电选择更为灵活，无需额外的外部电平转换器，简化了系统设计。这种高度灵活的供电管理减少了复杂性，并提高了系统的可靠性和整体性能。 AT91SAM9G45以其丰富的功能、高效的数据传输能力和优化的硬件架构，成为嵌入式系统开发的理想选择，特别适用于需要多媒体处理和高速通信的消费电子、工业自动化或物联网应用领域。

SAM9G45 [DATASHEET]

Atmel-6438M-ATARM-SAM9G45-Datasheet_13-Apr-15

5.1 Memory Mapping

A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of the Advanced

High performance Bus (AHB) for its Master and Slave interfaces with additional features.

Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 Mbytes. The banks 1 to 6 are directed to

the EBI that associates these banks to the external chip selects NCS0 to NCS5.

The bank 7 is directed to the DDRSDRC0 that associates this bank to DDR_NCS chip select and so dedicated to

the 4-port DDR2/ LPDDR controller.

The bank 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1

Mbyte of internal memory area. The bank 15 is reserved for the peripherals and provides access to the Advanced

Peripheral Bus (APB).

Other areas are unused and performing an access within them provides an abort to the master requesting such an

access.

5.2 Embedded Memories

5.2.1 Internal SRAM

The SAM9G45 product embeds a total of 64Kbytes high-speed SRAM split in 4 blocks of 16 Kbytes connected to

one slave of the matrix. After reset and until the Remap Command is performed, the four SRAM blocks are

contiguous and only accessible at address 0x00300000. After Remap, the SRAM also becomes available at

address 0x0.

Figure 5-2. Internal SRAM Reset

The SAM9G45 device embeds two memory features. The processor Tightly Coupled Memory Interface (TCM) that

allows the processor to access the memory up to processor speed (PCK) and the interface on the AHB side

allowing masters to access the memory at AHB speed (MCK).

A wait state is necessary to access the TCM at 400 MHz. Setting the bit NWS_TCM in the bus Matrix TCM

Configuration Register of the matrix inserts a wait state on the ITCM and DTCM accesses.

5.2.2 TCM Interface

On the processor side, this Internal SRAM can be allocated to two areas.

 Internal SRAM A is the ARM926EJ-S Instruction TCM. The user can map this SRAM block anywhere in the

ARM926 instruction memory space using CP15 instructions and the TCR configuration register located in

the Chip Configuration User Interface. This SRAM block is also accessible by the ARM926 Masters and by

the AHB Masters through the AHB bus

RAM

64K

0x00300000

RAM

64K

0x00000000

Remap

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