STM32F303RE-1：ARM Cortex-M4微控制器，全面技术规格

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STM32F303RE是一款基于ARM Cortex-M4内核的高性能32位微控制器，具有浮点运算单元（FPU）。这款设备的核心特性包括： 1. **处理器性能**: STM32F303RE搭载了72MHz的Cortex-M4 CPU，具备单周期乘法和硬件除法功能，提供高达90 DMIPS的计算能力，支持DSP指令集和内存保护单元（MPU），确保高效能和安全性。 2. **电源范围与电压管理**: 设备工作在2.0V至3.6V的宽广电压范围内，具有电源开/关复位（POR/PDR）功能，以及可编程电压检测器（PVD）用于低功耗操作。 3. **内存配置**: 内置512KB闪存，支持高达64KB的SRAM，其中前32KB配置有硬件奇偶校验。此外，还有16Kbyte的高速SRAM（Routine booster），专用于提升指令和数据处理性能，并同样支持奇偶校验。 4. **存储扩展**: 通过灵活的内存控制器（FSMC）接口，可以连接多个外部静态存储器，提供四个芯片选择线以实现多种存储选项。 5. **校验与安全**: 包含CRC（循环冗余校验）计算单元，确保数据传输的完整性。此外，还配备了用于实时时钟（RTC）和备份寄存器的备用电池供电（VBAT）。 6. **时钟系统**: 支持4到32MHz的外部晶振，以及一个32kHz的RTC专用晶体振荡器，带有校准功能。内部还有一个8MHz RC振荡器，可选配16倍频的锁相环（PLL）。 7. **低功耗模式**: 提供睡眠、停止和待机等多种低功耗模式，有助于优化电池续航或延长系统休眠时间。这款STM32F303RE微控制器因其丰富的功能、强大的处理能力和广泛的电压兼容性，适用于对性能和能源效率有较高要求的工业控制、嵌入式应用和物联网设备开发。开发者可以充分利用其内置的硬件加速器和低功耗特性，设计出高效能且能有效节省电力的解决方案。

Functional overview STM32F303xD STM32F303xE

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3 Functional overview

3.1 ARM

Cortex

-M4 core with FPU with embedded Flash and

SRAM

The ARM

Cortex

-M4 processor with FPU is the latest generation of ARM processors for

embedded systems. It was developed to provide a low-cost platform that meets the needs of

MCU implementation, with a reduced pin count and low-power consumption, while

delivering outstanding computational performance and an advanced response to interrupts.

The ARM

Cortex

-M4 32-bit RISC processor with FPU features exceptional code-

efficiency, delivering the high-performance expected from an ARM core in the memory size

usually associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions which allows efficient signal processing

and complex algorithm execution.

Its single precision FPU speeds up software development by using metalanguage

development tools, while avoiding saturation.

With its embedded ARM core, the STM32F303xD/E family is compatible with all ARM tools

and software.

Figure 1 shows the general block diagram of the STM32F303xD/E family devices.

3.2 Memory protection unit (MPU)

The memory protection unit (MPU) is used to separate the processing of tasks from the data

protection. The MPU manage up to 8 protection areas that are further divided up into 8

subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of

addressable memory.

The memory protection unit is especially helpful for applications where some critical or

certified code has to be protected against the misbehavior of other tasks. It is usually

managed by an RTOS (real-time operating system). If a program accesses a memory

location that is prohibited by the MPU, the RTOS detects it and takes action. In an RTOS

environment, the kernel dynamically updates the MPU area setting, based on the process to

be executed.

The MPU is optional and can be bypassed for applications that do not need it.

3.3 Embedded Flash memory

All STM32F303xD/E devices feature 384/512 Kbyte of embedded Flash memory available

for storing programs and data. The Flash memory access time is adjusted to the CPU clock

frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states

above).

Functional overview STM32F303xD STM32F303xE

18/173 DocID026415 Rev 5

3.7 Power management

3.7.1 Power supply schemes

• V

, V

= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. It is

provided externally through V

pins.

• V

SSA

, V

DDA

= 2.0 to 3.6 V: external analog power supply for ADC, DAC, comparators,

operational amplifier, reset blocks, RCs and PLL. The minimum voltage to be applied to

DDA

differs from one analog peripheral to another. Table 3 provides the summary of

the V

DDA

ranges for analog peripherals. The V

DDA

voltage level must always be greater

than or equal to the V

voltage level and must be provided first.

• V

BAT

= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and

backup registers (through power switch) when V

is not present.

3.7.2 Power supply supervisor

The device has an integrated power-on reset (POR) and power-down reset (PDR) circuits.

They are always active, and ensure proper operation above a threshold of 2 V. The device

remains in reset mode when the monitored supply voltage

is below a specified threshold,

POR/PDR, without the need for an external reset circuit.

• The POR monitors only the V

supply voltage. During the startup phase it is required

that V

DDA

should arrive first and be greater than or equal to V

• The PDR monitors both the V

and V

DDA

supply voltages, however the V

DDA

power

supply supervisor can be disabled (by programming a dedicated Option bit) to reduce

the power consumption if the application design ensures that V

DDA

is higher than or

equal to V

The device features an embedded programmable voltage detector (PVD) that monitors the

power supply and compares it to the VPVD threshold. An interrupt can be generated

when V

drops below the V

PVD

threshold and/or when V

is higher than the V

PVD

threshold. The interrupt service routine can then generate a warning message and/or put

the MCU into a safe state. The PVD is enabled by software.

3.7.3 Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR), and power-down.

• The MR mode is used in the nominal regulation mode (Run)

• The LPR mode is used in Stop mode.

• The power-down mode is used in Standby mode: the regulator output is in high

impedance, and the kernel circuitry is powered down thus inducing zero consumption.

The voltage regulator is always enabled after reset. It is disabled in Standby mode.

Table 3. External analog supply values for analog peripherals

Analog peripheral Minimum V

DDA

supply Maximum V

DDA

supply

ADC/COMP 2.0 V 3.6 V

DAC/OPAMP 2.4 V 3.6 V

DocID026415 Rev 5 19/173

STM32F303xD STM32F303xE Functional overview

3.7.4 Low-power modes

The STM32F303xD/E supports three low-power modes to achieve the best compromise

between low power consumption, short startup time and available wakeup sources:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and wake

up the CPU when an interrupt/event occurs.

• Stop mode

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC

and the HSE crystal oscillators are disabled. The voltage regulator can also be put

either in normal or in low-power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line

source can be one of the 16 external lines, the PVD output, the USB wakeup, the RTC

alarm, COMPx, I2Cx or U(S)ARTx.

• Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup

domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a

rising edge on the WKUP pin or an RTC alarm occurs.

Note: The RTC, the IWDG and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

3.8 Interconnect matrix

Several peripherals have direct connections between them. This allows autonomous

communication between peripherals, saving CPU resources thus power supply

consumption. In addition, these hardware connections allow fast and predictable latency.

Table 4. STM32F303xD/E peripheral interconnect matrix

Interconnect source

Interconnect

destination

Interconnect action

TIMx

TIMx Timers synchronization or chaining

ADCx

DAC1

Conversion triggers

DMA Memory to memory transfer trigger

Compx Comparator output blanking

COMPx TIMx Timer input: OCREF_CLR input, input capture

ADCx TIMx Timer triggered by analog watchdog

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