BCM5396：单芯片16端口SerDes千兆交换机数据表

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"BCM5396 5396-DS109-R Data Sheet" BCM5396是一款由Broadcom Corporation设计的单芯片16端口串行千兆交换机，其主要特点在于其集成性高和成本效益。这款器件在11/13/2007发布的先进数据表中详细描述，提供了针对桌面交换解决方案或WebSmart应用的低功耗GbE（千兆以太网）功能。 **关键技术点：** 1. **16个1.25G SerDes/SGMII端口接口**：BCM5396集成了16个1.25Gbps的SerDes（串行收发器）/ SGMII（串行千兆媒体独立接口）端口，这使得它可以与外部的千兆物理层（PHY）设备或光纤模块进行连接，支持高速数据传输。 2. **高度集成**：该芯片将高速交换系统所需的所有功能如包缓冲、媒体访问控制器（MACs）、地址管理以及非阻塞式交换控制器整合进一个单一的0.13微米CMOS（互补金属氧化物半导体）封装中。这种集成度降低了硬件成本并提高了系统效率。 3. **符合IEEE标准**：BCM5396遵循IEEE 802.3系列标准，包括802.3u（Fast Ethernet）、802.3ab（1000BASE-T）和802.3x（流量控制），确保与所有行业标准的以太网、快速以太网和千兆以太网设备的兼容性。 4. **MAC控制PAUSE帧和自动协商**：支持802.3x规定的MAC控制PAUSE帧，允许网络设备根据需要动态调整数据流，从而避免拥塞。同时，自动协商功能使设备能够检测并匹配与其相连的对端设备的最佳速度和双工模式。 5. **非阻塞交换控制器**：BCM5396采用非阻塞设计，意味着在网络负载极高的情况下，所有端口之间仍能实现全带宽的无损通信，保证了网络性能。 6. **WebSmart功能**：WebSmart是一种智能网络设备，通常包含基本的管理和监控功能，允许用户通过Web界面进行配置和故障排查，简化了网络管理和维护。 **应用场景：** BCM5396适用于桌面级交换机和WebSmart应用，这些场景需要高效能、低成本且易于管理的网络解决方案。例如，企业内部的局域网扩展、数据中心内部的高速连接、以及家庭和小型办公室的网络基础设施建设等。 BCM5396是现代网络基础设施中的关键组件，它以紧凑的封装、丰富的功能和良好的兼容性，满足了各种千兆以太网网络环境的需求。

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BCM5396 Advance Data Sheet

11/13/07

Broadcom Corporation

Page xvi Document 5396-DS109-R

LIST OF TABLES

Table 1: Frame Priority Decision Tree Summary ............................................................................................. 5

Table 2: Bucket Bit Rate ................................................................................................................................10

Table 3: Unicast Forward Field Definitions ....................................................................................................16

Table 4: Address Table Entry for Unicast Address ........................................................................................17

Table 5: Multicast Forward Field Definitions ..................................................................................................18

Table 6: Address Table Entry for Multicast ARL Address ..............................................................................18

Table 7: Behavior for Reserved Multicast Addresses ....................................................................................19

Table 8: Spanning Tree State ........................................................................................................................23

Table 9: SGMII and SerDes Auto-Negotiation ...............................................................................................31

Table 10: Transmit/Receive Frame Format Over Management Port ...............................................................33

Table 11: OPCODE Field in BRCM Tag for Management Port Frame ............................................................34

Table 12: IMP Broadcom TAG RX from CPU ..................................................................................................34

Table 13: IMP Broadcom TAG TX to CPU.......................................................................................................34

Table 14: EEPROM_EXT[1:0] Settings............................................................................................................42

Table 15: EEPROM Header Format ................................................................................................................43

Table 16: EEPROM Contents ..........................................................................................................................43

Table 17: Pseudo-PHY MII Register Definitions ..............................................................................................48

Table 18: MII Management Frame Format ......................................................................................................49

Table 19: Serial LED Mode Matrix ...................................................................................................................50

Table 20: Serial LED Status Types ..................................................................................................................51

Table 21: Load Meter LED Decode..................................................................................................................51

Table 22: I/O Signal Type Definitions...............................................................................................................52

Table 23: Signal Descriptions ..........................................................................................................................53

Table 24: Pin Assignment (Listed by Pin Number) ..........................................................................................58

Table 25: Pin Assignment (Listed by Signal Name).........................................................................................60

Table 26: Global Page Register Map ...............................................................................................................63

Table 27: Control Registers (Page 00h)...........................................................................................................66

Table 28: 10/100/1000 Port Control Register (Page 00h: Address 00h–0Fh) ................................................. 67

Table 29: IMP Port Control Register (Page 00h: Address 10h) .......................................................................68

Table 30: Switch Mode Register (Page 00h: Address 20h) .............................................................................69

Table 31: LED A Register (Page 00h: Address 24h–25h) ............................................................................... 69

Table 32: New Control Register (Page 00h: Address 3Bh)..............................................................................70

Table 33: Reserved Multicast Register (Page 00h: Address 50h) ...................................................................70

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Advance Data Sheet BCM5396

11/13/07

Broadcom Corporation

Document 5396-DS109-R Page xvii

Table 34: Load Meter Update Rate Control Register (Page 00h: Address 51h) ............................................. 71

Table 35: Unicast Lookup Failed Forward Map Register (Page 00h: 54h–57h).............................................. 71

Table 36: Multicast Lookup Failed Forward Map Register (Page 00h: Address 58h–5Bh) ............................. 71

Table 37: Port N State Override Register (Page 00h: Address 60–6Fh)......................................................... 72

Table 38: Port 16 (IMP) State Override Register (Page 00h: Address 70h).................................................... 72

Table 39: 802.1X Control Register 1 (Page 00h: Address 77h) ......................................................................73

Table 40: 802.1X Control Register 2 (Page 00h: Address 78h–7Bh) .............................................................. 73

Table 41: SerDes Default Values Register (Page 00h: Address 80h–83h) ..................................................... 73

Table 42: SerDes Select Early Version of CRS and COL Register (Page 00h: Address 84h–85h) ................ 73

Table 43: External PHY Scan Control Register (Page 00h: Address 86h) ...................................................... 74

Table 44: Fast Aging Control Register (Page 00h: Address 88h)....................................................................74

Table 45: Fast Aging Port Register (Page 00h: Address 89h)......................................................................... 74

Table 46: Fast Aging VID Register (Page 00h: Address 138d–139d, 8Ah–8Bh) ............................................ 75

Table 47: Pause Frame Detection Control Register (Page 00h: Address 90h) ............................................... 75

Table 48: Status Registers (Page 01h)............................................................................................................ 76

Table 49: Link Status Summary Register (Page 01h: Address 00h–03h) ....................................................... 77

Table 50: Link Status Change Register (Page 01h: Address 04h–07h) .......................................................... 77

Table 51: Port Speed Summary Register (Page 01h: Address 08h–0Fh)....................................................... 77

Table 52: Duplex Status Summary Register (Page 01h: Address 10h–13h)................................................... 78

Table 53: TX PAUSE Status Summary Register (Page 01h: Address 14h–17h) ............................................ 78

Table 54: RX PAUSE Status Summary Register (Page 01h: Address 18h–1Bh) ........................................... 78

Table 55: Port N PHY Status Register (Page 01h: Address 20–2Fh) ............................................................. 79

Table 56: SerDes Signal Detect Status Register (Page 01h: Address 40h).................................................... 79

Table 57: BIST Status Register (Page 01h, Address 46h) .............................................................................. 79

Table 58: Strap Value Register (Page 01h: Address 70h–73h).......................................................................79

Table 59: Management Mode Registers (Page 02h)....................................................................................... 81

Table 60: Global Management Configuration Register (Page 02h: Address 00h)........................................... 81

Table 61: Aging Time Control Register (Page 02h: Address 0Ch–0Fh).......................................................... 82

Table 62: Mirror Capture Control Register (Page 02h: Address 10h–11h)...................................................... 82

Table 63: Ingress Mirror Control Register (Page 02h: Address 12h–15h)....................................................... 83

Table 64: Ingress Mirror Divider Register (Page 02h: Address 16h–17h) ....................................................... 83

Table 65: Egress Mirror Control Register (Page 02h: Address 1Ch–1Fh) ...................................................... 83

Table 66: Model ID Register (Page 02h: Address 30h) ................................................................................... 84

Table 67: Revision ID Register (Page 02h: Address 40h) ............................................................................... 84

Table 68: ARL Control Registers (Page 04h) .................................................................................................. 85

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Broadcom Corporation

Page xviii Document 5396-DS109-R

Table 69: Global ARL Configuration Register (Page 04h: Address 00h) .........................................................85

Table 70: BPDU Multicast Address Register (Page 04h: Address 04h–09h) ..................................................86

Table 71: Multiport Address 1 Register (Page 04h: Address 10h–15h)...........................................................86

Table 72: Multiport Vector 1 Register (Page 04h: Address 16h–19h).............................................................. 86

Table 73: Multiport Address 2 Register (Page 04h: Address 20h–25h)...........................................................87

Table 74: Multiport Vector 2 Register (Page 04h: Address 26h–29h).............................................................. 87

Table 75: ARL/VTBL Access Registers (Page 05h).........................................................................................88

Table 76: ARL Read/Write Control Register (Page 05h: Address 00h) ........................................................... 88

Table 77: MAC Address Index Register (Page 05h: Address 02h–07h)..........................................................89

Table 78: VID Index Register (Page 05h: Address 08h–09h) ..........................................................................89

Table 79: ARL MAC/VID Entry 0 Register (Page 05h: Address 10h–17h) ......................................................89

Table 80: ARL FWD Entry 0 Register (Page 05h: Address 18h–1Bh) .............................................................90

Table 81: ARL MAC/VID Entry 1 Register (Page 05h: Address 20h–27h) ......................................................91

Table 82: ARL FWD Entry 1 Register (Page 05h: Address 28h–2Bh) .............................................................91

Table 83: ARL Search Control Register (Page 05h: Address 30h)..................................................................92

Table 84: ARL Search Address Register (Page 05h: Address 31h–32h) ........................................................92

Table 85: ARL Search MAC/VID Result Register0 (Page 05h: Address 33h–3Ah).........................................93

Table 86: ARL Search Result Register 0 (Page 05h: Address 3Bh–3Eh) .......................................................93

Table 87: ARL Search MAC/VID Result Register 1 (Page 05h: Address 40h–47h) ........................................94

Table 88: ARL Search Result Register 1 (Page 05h: Address 48h–4Bh)........................................................94

Table 89: VTBL Read/Write Control Register (Page 05h: Address 60h) .........................................................95

Table 90: VTBL Address Index Register (Page 05h: Address 61h–62h).........................................................95

Table 91: VTBL Entry Register (Page 05h: Address 63h–6Ah) .......................................................................95

Table 92: Flow Control Registers (Page 0Ah)..................................................................................................96

Table 93: Internal SerDes Registers Page Descriptions 10h–1Fh.................................................................100

Table 94: Internal SerDes Registers Page 10h–1Fh .....................................................................................100

Table 95: MII Control (Page 10h–1Fh: Address 00h–01h) ............................................................................102

Table 96: MII Status (Page 10h–1Fh: Address 02h–03h)..............................................................................103

Table 97: Auto-Negotiation Advertisement (Page 10h–1Fh: Address 08h–09h) ...........................................104

Table 98: Auto-Negotiation Link Partner Ability (Page 10h–1Fh: Address 0Ah–0Bh) ...................................105

Table 99: Auto-Negotiation Expansion (Page 10h–1Fh: Address 0Ch–0Dh) ................................................106

Table 100:Extended Status (Page 10h–1Fh: Address 1Eh–1Fh) ...................................................................106

Table 101:SerDes/SGMII Control1 (Page 10h–1Fh: Address 20h–21h, Block 0) ..........................................107

Table 102:Analog Transmit register (page 10h ~ 1Fh: Address 20h ~ 21h, Block 1) .....................................109

Table 103:SerDes/SGMII Control 2 (Page 10h–1Fh: Address 22h–23h) .......................................................110

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Advance Data Sheet BCM5396

11/13/07

Broadcom Corporation

Document 5396-DS109-R Page xix

Table 104:SerDes/SGMII Control 3 (Page 10h–1Fh: Address 24h–25h)....................................................... 111

Table 105:SerDes/SGMII Status 1 (Page 10h–1Fh: Address 28h–29h) ........................................................ 111

Table 106:SerDes/SGMII Status 2 (Page 10h–1Fh: Address 2Ah–2Bh) ....................................................... 112

Table 107:SerDes/SGMII Status 3 (Page 10h–1Fh: Address 2Ch–2Dh)....................................................... 113

Table 108:BER/CRC Error Counter Register (Page 10h ~ 1Fh: Address 2Eh ~ 2Fh) ................................... 115

Table 109:PRBS Control Register (Page 10h ~ 1Fh: Address 30h ~ 31h) .................................................... 115

Table 110:PRBS Control Register (Page 10h ~ 1Fh: Address 32h ~ 33h) .................................................... 116

Table 111:Pattern Generator Control Register (Page 10h ~ 1Fh: Address 34h ~ 35h) ................................. 116

Table 112:Pattern Generator Control Register (Page 10h ~ 1Fh: Address 36h ~ 37h) ................................. 117

Table 113:Pattern Generator Control Register (Page 10h ~ 1Fh: Address 36h ~ 37h) ................................. 118

Table 114:Force Transmit 1 Register (Page 10h ~ 1Fh: Address 3Ah ~ 3Bh)............................................... 118

Table 115:Block Address (Pages 10h–1Fh: Address 3Eh ~ 3Fh) .................................................................. 118

Table 116:QoS Registers (Page 30h) ............................................................................................................ 119

Table 117:QoS Global Control Register (Page 30h: Address 00h) ................................................................ 120

Table 118:QoS Threshold Control Register (Page 30h: Address 01h–02h) .................................................. 120

Table 119:QoS 1P Enable Register (Page 30h: Address 04h–07h) .............................................................. 120

Table 120:QoS DiffServ Enable Register (Page 30h: Address 08h–0Bh)...................................................... 121

Table 121:1P/1Q Priority Map Register (Page 30h: Address 10h–13h)......................................................... 121

Table 122:DiffServ Priority Map 0 Register (Page 30h: Address 30h–35h) ................................................... 121

Table 123:DiffServ Priority Map 1 Register (Page 30h: Address 36h–3Bh)................................................... 122

Table 124:DiffServ Priority Map 2 Register (Page 30h: Address 3Ch–41h)................................................... 122

Table 125:DiffServ Priority Map 3 Register (Page 30h: Address 42h–47h) ................................................... 123

Table 126:QoS Port Control N Register (Page 30h: Address 50h–71h) ........................................................ 123

Table 127:QoS TX Control Register (Page 30h: Address 80h)...................................................................... 124

Table 128:Queue N Weight Register (Page 30h: Address 81h–84h)............................................................. 124

Table 129:EtherType Priority Control Register (Page 30h: Address 88h–8Bh) ............................................. 124

Table 130:Enable Traffic Priority Remap Control Register (Page 30h: Address A0h–A3h)........................... 125

Table 131:Traffic Priority Remap Register (Page 30h: Address A4h) ............................................................ 125

Table 132:Page 31h Port-based VLAN Registers .......................................................................................... 126

Table 133:Port VLAN Control Register (Pages: 31h, Address 0h–43h)......................................................... 126

Table 134:Trunking Registers (Page 32h)...................................................................................................... 127

Table 135:MAC Trunk Control Register (Pages: 32h, Address 1h)................................................................ 128

Table 136:Trunk Group Register [0:3] (Pages: 32h, Address 90h–9Fh) ........................................................ 128

Table 137:QoS Registers (Page 34h) ............................................................................................................ 129

Table 138:Global Control 0 Register (Pages 34h: Address 00h) ................................................................... 130

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BCM5396 Advance Data Sheet

11/13/07

Broadcom Corporation

Page xx Document 5396-DS109-R

Table 139:Global Control 1 Register (Pages 34h: Address 01h)....................................................................130

Table 140:Global Control 2 Register (Pages 34h: Address 02h)....................................................................131

Table 141:Global Control 3 Register (Pages 34h: Address 03h–06h) ............................................................131

Table 142:Global Control 4 Register (Pages 34: Address 07h)......................................................................131

Table 143:Global Control 5 Register (Pages 34h: Address 08h)....................................................................132

Table 144:New Priority Map Register (Pages 34h: Address 0C–0Fh)............................................................133

Table 145:Port N Default 802.1Q Tag Register (Pages 34h: Address 10h–31h) ...........................................133

Table 146:Jumbo Frame Control Registers (Page 40h) ................................................................................. 134

Table 147:Jumbo Frame Port Mask Registers (Pages 40h: Address 01h–04h)............................................. 134

Table 148:Broadcast Storm Suppression Registers (Page 41h) ....................................................................135

Table 149:Suppression Control Registers (Pages 41h: Address 00h–03h)....................................................136

Table 150:Port N Receive Rate Control Registers (Pages 41h: Address 10h–4Fh).......................................137

Table 151:Port N Suppressed Packet Drop Counter Register (Pages 41h: Address 80h–9Fh).....................138

Table 152:IEEE Standard 802.1s Multiple Spanning Tree Registers (Page 43h)...........................................139

Table 153:Multiple Spanning Tree Control Register (Pages 43h: Address 00h) ............................................140

Table 154:MST Table Registers (Page 43h: Address 10h–CFh)....................................................................140

Table 155:External PHY Registers (Serial Ports) Page Summary..................................................................143

Table 156:External PHY Registers (Serial Ports) (Page 80h–87h)................................................................. 143

Table 157:Global Registers (Maps to All Pages) ............................................................................................145

Table 158:SPI Data I/O Register (Maps to All Registers, Address F0–F7h)................................................... 145

Table 159:SPI Status Register (Maps to All Registers, Address FEh)............................................................145

Table 160:Page Register (Maps to All Registers, Address FFh) ....................................................................145

Table 161:Absolute Maximum Ratings ...........................................................................................................146

Table 162:Recommended Operating Conditions ............................................................................................146

Table 163:Electrical Characteristics................................................................................................................147

Table 164:SerDes Electrical Characteristics...................................................................................................148

Table 165:Reset and Clock Timing .................................................................................................................149

Table 166:RvMII Mode Output Timings ..........................................................................................................150

Table 167:RvMII Mode Input Timings .............................................................................................................151

Table 168:RGMII Output Timing (Normal Mode) ............................................................................................152

Table 169:RGMII Output Timing (Delayed Mode) ..........................................................................................153

Table 170:RGMII Input Timing (Normal Mode)...............................................................................................154

Table 171:RGMII Input Timing (Delayed Mode) .............................................................................................155

Table 172:GMII Output Timing........................................................................................................................156

Table 173:GMII Input Timing ..........................................................................................................................157

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