低功耗数字IC设计指南：从入门到精通

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"IC低功耗设计是数字集成电路领域中的关键课题，对于电子工程师无论是初级学习还是进阶研究都具有重要价值。本指南——Synopsys® Low-Power Flow User Guide Version B-2008.09，发布于2008年9月，由Synopsys公司编撰，旨在提供一套系统的方法论来优化芯片设计，减少功耗，这对于现代电子设备的节能和可持续性至关重要。在低功耗设计过程中，设计师需关注以下几个核心要素： 1. 设计策略：理解并应用有效的电源管理技术，如动态电压频率调节（DVFS）、时钟门控、电路优化等，这些方法能够显著降低芯片在不同工作模式下的能量消耗。 2. 工具利用：Synopsys的低功耗流（Low-Power Flow）是一个集成的工具套件，它提供了完整的流程，从建模到实现，帮助设计师在设计初期就考虑到功耗问题，并在每个阶段进行优化。 3. 仿真与分析：通过使用像电源噪声分析、功耗预测工具等，可以评估设计的功耗特性，确保在满足性能需求的同时，实现最小化的功耗。 4. 版权与许可：在使用此类工具和文档时，必须遵守严格的版权协议。用户只能根据授权协议复制和使用文档，不得擅自复制、传播或翻译，除非获得Synopsys公司的书面许可或授权条款明确允许。 5. 交流与支持：遇到问题时，可以通过访问Solvnet.synopsys.com，进入支持中心提交评论，获取来自Synopsys的专业技术支持。低功耗设计不仅考验工程师的技术技能，还要求他们具备对市场趋势的理解，因为随着物联网(IoT)和移动设备的普及，电池续航和能效已经成为消费者选择产品的重要因素。因此，持续学习和掌握这些技术对于电子行业的未来发展至关重要。总结来说，这本用户指南提供了实用的工具和技术，使IC设计者能够在设计初期就充分考虑功耗，从而实现高性能和低能耗的平衡，这对整个半导体行业的发展以及环境保护都有着深远的影响。"

1-4

Chapter 1: Low-Power Design Strategies

Figure 1-2 Internal Power

Static (Leakage) Power

Leakage current was negligible in earlier CMOS technologies. However, with shrinking

device geometries and reduced threshold voltages, leakage power is becoming increasingly

significant, sometimes approaching the levels of dynamic power dissipation.

The main causes of leakage power are reverse-bias p-n junction diode leakage, sub-

threshold leakage, and gate leakage. These leakage paths in a CMOS inverter are shown in

Figure 1-3.

Figure 1-3 Static Leakage Currents

Intermediate

voltage

Short-circuit

(crowbar)

current

Off

Gate

leakage

p-n junction

leakage to

substrate

Sub-threshold

leakage

Off

Gate

leakage

p-n junction

leakage from

n-well

Sub-threshold

leakage

1-5

Power Reduction Methods

Leakage at reverse-biased p-n junctions (diode leakage) has always existed in CMOS

circuits. This is the leakage from the n-type drain of the NMOS transistor to the grounded p-

type substrate, and from the n-well (held at VDD) to the p-type drain of the PMOS transistor.

This leakage is relatively small.

Sub-threshold leakage is the small source-to-drain current that flows even when the

transistor is held in the “off” state. In older technologies, this current was negligible. However,

with lower power supply voltages and lower threshold voltages, “off” gate voltages are

getting close to “on” threshold voltages. Sub-threshold leakage current increases

exponentially as the gate voltage approaches the threshold voltage.

Gate leakage is the result of using an extremely thin insulating layer between the gate

conductor and the MOS transistor channel. Gate oxides are becoming so thin that only a

dozen or fewer layers of insulating atoms separate the gate from the source and drain. Under

these conditions, quantum-effect tunneling of electrons through the gate oxide can occur,

resulting in significant leakage from the gate to the source or drain.

Leakage currents occur whenever power is applied to the transistor, irrespective of the clock

speed or switching activity. Leakage cannot be reduced by slowing or stopping the clock.

However, it can be reduced or eliminated by lowering the supply voltage or by switching off

the power to the transistors entirely.

Power Reduction Methods

There are several different RTL and gate-level design strategies for reducing power. Some

methods, such as clock gating, have been used widely and successfully for many years.

Others, such as dynamic voltage and frequency scaling, have not been used much in the

past due to the difficultly of implementing them. As power becomes increasingly important

in advanced technologies, more methods are being exploited to achieve the design

requirements.

Supply Voltage Reduction

The most basic way to reduce power is to reduce the supply voltage. Power usage is

proportional to the square of the supply voltage, as the simple example in Figure 1-4

demonstrates. A 50 percent reduction in the supply voltage results in a 50 percent reduction

in current and a 75 percent reduction in power. A similar degree of power reduction can be

achieved in CMOS circuits for both dynamic and static power.

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