ATMEGA8：高性能单片机开发指南

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ATMEGA8是一款高性能、低功耗的AVR单片机，它基于先进的RISC架构，提供了高效能的计算能力。这款8位微控制器具有130条强大的指令，其中大部分可以在一个时钟周期内执行，这显著提升了程序执行速度。它配备了32个8位通用工作寄存器，支持完全静态操作，能够在16MHz时钟下实现高达16MIPS的处理性能，内置了2周期乘法器，提高了计算效率。非易失性存储器是ATMEGA8的重要特性，包括8KB的可系统编程闪存，能够承受高达10,000次写入/擦除循环，确保了长期的数据存储稳定性。此外，还提供了一个可独立锁定的引导代码区域，以及在芯片上进行的自内程序功能，支持真正的读写操作。存储器还包括512字节的EEPROM，具有100,000次写入/擦除循环的耐久度，以及1KB的内部SRAM，增强了数据存储和处理灵活性，并提供了软件安全的编程锁定功能。在外设方面，ATMEGA8拥有丰富的功能。它包含两个独立预分频器的8位定时器/计数器，其中一个支持比较模式。还有一个具有独立预分频器、比较模式和捕获模式的16位定时器/计数器，非常适合精确的时间管理。另外，还有一个实时计数器，配备独立的时钟源，为精确的时间同步提供了条件。ATMEGA8还配置了三个PWM通道，用于脉宽调制控制，这对于电机驱动和电源管理等应用非常实用。在模拟输入方面，ATMEGA8提供了多通道ADC，包括6个10位精度的ADC（在TQFP和MLF封装下）和2个8位精度的ADC（同样在TQFP封装），以及4个10位精度的ADC（在PDIP封装下）和2个8位精度的ADC，适应不同精度的信号测量需求。这些ADC支持字节导向的接口，简化了数据采集过程。 ATMEGA8凭借其高性能、丰富的外设和灵活的存储选项，是嵌入式系统开发的理想选择，适用于各种需要高效能和精确控制的应用，如工业自动化、消费电子和物联网设备。通过深入理解和利用这些特性，开发人员可以构建出高效、可靠的智能设备。

ATmega8(L)

2486M–AVR–12/03

SRAM Data Memory Figure 8 shows how the ATmega8 SRAM Memory is organized.

The lower 1120 Data memory locations address the Register File, the I/O Memory, and

the internal data SRAM. The first 96 locations address the Register File and I/O Mem-

ory, and the next 1024 locations address the internal data SRAM.

The five different addressing modes for the Data memory cover: Direct, Indirect with

Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In

the Register File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base

address given by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-

increment, the address registers X, Y and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, and the 1024 bytes of inter-

nal data SRAM in the ATmega8 are all accessible through all these addressing modes.

The Register File is described in “General Purpose Register File” on page 10.

Figure 8. Data Memory Map

R29

R30

R31

I/O Registers

$00

$01

$02

...

$3D

$3E

$3F

...

$0000

$0001

$0002

$001D

$001E

$001F

$0020

$0021

$0022

...

$005D

$005E

$005F

...

Data Address Space

$0060

$0061

$045E

$045F

...

Internal SRAM

ATmega8(L)

2486M–AVR–12/03

The EEPROM Address

• Bits 15..9 – Res: Reserved Bits

These bits are reserved bits in the ATmega8 and will always read as zero.

• Bits 8..0 – EEAR8..0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL – specify the EEPROM

address in the 512 bytes EEPROM space. The EEPROM data bytes are addressed lin-

early between 0 and 511. The initial value of EEAR is undefined. A proper value must be

written before the EEPROM may be accessed.

The EEPROM Data Register –

EEDR

• Bits 7..0 – EEDR7..0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written to

the EEPROM in the address given by the EEAR Register. For the EEPROM read oper-

ation, the EEDR contains the data read out from the EEPROM at the address given by

EEAR.

The EEPROM Control

• Bits 7..4 – Res: Reserved Bits

These bits are reserved bits in the ATmega8 and will always read as zero.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set.

Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a

constant interrupt when EEWE is cleared.

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be

written. When EEMWE is set, setting EEWE within four clock cycles will write data to the

EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect.

When EEMWE has been written to one by software, hardware clears the bit to zero after

four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.

• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When

address and data are correctly set up, the EEWE bit must be written to one to write the

Bit 15 14 13 12 11 10 9 8

– – – – – – – EEAR8 EEARH

EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

7 6 5 4 3 2 1 0

Read/Write R R R R R R R R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 X

X X X X X X X X

Bit 7 6 5 4 3 2 1 0

MSB LSB EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

– – – – EERIE EEMWE EEWE EERE EECR

Read/Write R R R R R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 X 0

ATmega8(L)

2486M–AVR–12/03

value into the EEPROM. The EEMWE bit must be written to one before a logical one is

written to EEWE, otherwise no EEPROM write takes place. The following procedure

should be followed when writing the EEPROM (the order of steps 3 and 4 is not

essential):

1. Wait until EEWE becomes zero.

2. Wait until SPMEN in SPMCR becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.

6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The

software must check that the Flash programming is completed before initiating a new

EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing

the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2

can be omitted. See “Boot Loader Support – Read-While-Write Self-Programming” on

page 206 for details about boot programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the

EEPROM Master Write Enable will time-out. If an interrupt routine accessing the

EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be

modified, causing the interrupted EEPROM access to fail. It is recommended to have

the Global Interrupt Flag cleared during all the steps to avoid these problems.

When the write access time has elapsed, the EEWE bit is cleared by hardware. The

user software can poll this bit and wait for a zero before writing the next byte. When

EEWE has been set, the CPU is halted for two cycles before the next instruction is

executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the

correct address is set up in the EEAR Register, the EERE bit must be written to a logic

one to trigger the EEPROM read. The EEPROM read access takes one instruction, and

the requested data is available immediately. When the EEPROM is read, the CPU is

halted for four cycles before the next instruction is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation

is in progress, it is neither possible to read the EEPROM, nor to change the EEAR

The calibrated Oscillator is used to time the EEPROM accesses. Table 1 lists the typical

programming time for EEPROM access from the CPU.

Note: 1. Uses 1 MHz clock, independent of CKSEL Fuse settings.

Table 1. EEPROM Programming Time

Symbol

Number of Calibrated RC

Oscillator Cycles

(1)

Typ Programming Time

EEPROM Write (from CPU) 8448 8.5 ms

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