McPATAlpha：多核处理器设计的功耗-面积-时序综合模拟框架

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McPATAlpha_TechRep.pdf是一份关于多核处理器设计中的关键性能指标（如功耗、面积和时序）综合建模框架的论文。这份技术报告介绍了McPAT1.0，一个针对从90纳米到22纳米以及更先进工艺节点的多功能设计空间探索工具。在微观架构层面，McPAT涵盖了芯片多处理器的核心组件，包括顺序执行和乱序执行的处理器核心、片上网络（NoC）、共享缓存、集成内存控制器以及多域时钟系统。该模型框架在以下几个关键方面提供支持： 1. 处理器核心建模：区分了顺序执行和乱序执行的处理逻辑，这些是决定系统性能的关键组成部分，对于理解不同指令调度策略对能效的影响至关重要。 2. 片上网络（NoC）建模：NoC负责连接处理器核心，影响数据传输效率和能耗。McPAT通过精确模拟NoC结构和通信协议，优化核心间的协同工作。 3. 缓存和内存控制器建模：共享缓存的设计和管理对整个系统的功耗有显著影响，McPAT通过考虑数据访问模式和命中率来估计这部分的能耗。 4. 电路和技术层面：McPAT针对ITRS（国际半导体技术路线图）预测的各种器件类型，如CMOS、SOI（绝缘体上硅）和双栅极晶体管，提供了详细的电路级和技术层的模型。这涵盖了关键路径时序分析、电路面积估算以及动态功耗（包括短路和漏电）的计算。 5. 可扩展性和灵活性：McPAT采用灵活的XML接口设计，便于与各种设计工具和流程集成，提高了模型的适用性和效率，使得设计者能够在不同设计阶段方便地应用和调整模型参数。 McPAT1.0是一个强大的设计辅助工具，它结合了微架构、电路和技术层面的模型，帮助设计师在多核和许多核心处理器的设计过程中进行全面而精细的功耗、面积和时序分析，从而优化系统性能，降低功耗，并适应不断发展的技术趋势。这份文档对于那些关注高性能、低功耗SoC设计的专业人士来说，具有很高的参考价值和实用意义。

the statistics, namely, the activity factors of each individual components to McPAT via the XML interface ﬁle. As

shown in Equation 1, the activity factor of a component is the product of access count of the component and the average

hamming distance of all accesses for the time interval. By changing the time interval, one can change the granularity

of runtime power computation. If the performance simulator calls McPAT for runtime power computation every cycle,

a cycle accurate power consumption proﬁle will be generated, which will be useful to study realtime power spikes. If

the performance simulator calls McPAT for runtime power computation after power simulation is complete, an averaged

power proﬁle will be generated.

ActivityFactor = (AccessCount ∗ ((

∑

i=1

HammingDistance)/n))/n (1)

In Equation 1, n is the cycle count for a given simulation period, AccessCount is the number of accesses to a speciﬁc

component during the period, and the HammingDistance is the total number of ﬂipped bits for two consecutive accesses.

If the performance simulator cannot track the Hamming Distance, McPAT assumes that all bits are ﬂipped per cycle.

It is always best for the performance simulator can provide the activity factor for each individual component, however,

McPAT also has the ability to reason about activity factors for components as long as the basic statistics information

is provided by the performance simulator. For example, if the performance simulator can only track the number of

memory instructions rather than the detailed information of activity factors of the load or store queue, McPAT assumes

that each memory instruction will involve one read, one write, and one or two search operations (depends on the hardware

speciﬁcation) on load and store queues. This assumption is made based on the default implementations of the load and

store unit as discussed later in this report.

McPAT runs separately from a performance simulator and only reads performance statistics from it — therefore,

its impact on the simulation speed of the native performance simulator is minimal. Although the initialization phase

of McPAT may take some time to complete because of the huge search space, it will not affect the simulator speed

signiﬁcantly since it needs to be done only once at the beginning of the simulation. During the computation phase, some

simulator overhead may result from added performance counters.

3 Integrated and Hierarchical Modeling Framework

In order to model the power, area, and timing of a multicore processor, McPAT takes an integrated and hierarchical

approach. It is integrated in that McPAT models power, area, and timing simultaneously. Because of this McPAT is able

to ensure that the results are mutually consistent from an electrical standpoint. It is hierarchical in that it decomposes

the models into three levels: architectural, circuit, and technology level. This provides users with the ﬂexibility to model

a broad range of possible multicore conﬁgurations across multiple implementation technologies. Taken together, this

integrated and hierarchical approach enables the user to paint a comprehensive picture of a design space, exploring

tradeoffs between design and technology choices in terms of power, area, and timing.

3.1 Power Modeling

As shown in Equation (2), power dissipation of CMOS circuits has three main components: dynamic, short-circuit, and

leakage power. All three contribute signiﬁcantly to the total power dissipation of multicore processors fabricated using

a deep-submicron technology.

total

= αCV

∆V f

clk

| {z }

Dynamic

short circuit

| {z }

Short circuit

leakage

| {z }

Leakage

(2)

The ﬁrst term is the dynamic power that is spent in charging and discharging the capacitive loads when the circuit

switches state, where C is the total load capacitance, V

is the supply voltage, ∆V is the voltage swing during switching,

and f

clk

is the clock frequency. C depends on the circuit design and layout of each IC component; we calculate it using

analytic models for regular structures such as memory arrays and wires, along with empirical models for random logic

structures such as ALUs. The activity factor α indicates the fraction of total circuit capacitance being charged during a

clock cycle. We calculate α using access statistics from architectural simulation together with circuit properties.

The second term is the short-circuit power that is consumed when both the pull-up and pull-down devices in a

CMOS circuit are partially on for a small, but ﬁnite amount of time. Short-circuit power is about 10% of the total

dynamic power, however it has been reported that the short-circuit power can be approximately 25% of the dynamic

power in some cases [42, 62]. When circuit blocks switch, they consume both dynamic and short-circuit power. The

inherent circuit property determines the ratio of the short-circuit power to the dynamic power, which is a strong function

of the V

to V

ratio. Since the V

to V

ratio shrinks for future low power designs, short-circuit power is expected to

become more signiﬁcant in future designs that require lower power and longer battery life. We compute the short-circuit

energy per switch of a gate, using the Equations 3 to 5 derived in [42].

<<τ)

>>τ)

(3)

<< τ) =

∗

(0.5 − v

)

(4)

>> τ) =

(0.5 − v

)

3/2

10 ∗ 2

+2α

(5)

Here, E

<< τ) is the short circuit energy per switch of a gate with slow input, while E

<< τ) is the short

circuit energy per switch of a gate with fast input, v

is the normalized threshold voltage (V

), α is the velocity

saturation index which is close to one at deep sub-micron technology, C

is the input capacitance of the gate, V

is the

supply voltage, f

is the transistor driveability ratio of succeeding gates, and F

is fanout (C

out

The third term is the static power consumed due to leakage current through the transistors, which in reality function

as “imperfect” switches. There are two distinct leakage mechanisms, and the magnitude of each leakage current is

proportional to the width of the transistor and depends on the logical state of the device. The ﬁrst type of leakage,

subthreshold leakage, occurs when a transistor that is supposedly in the off state actually allows a small current to pass

between its source and drain. We let I

sub

denote the subthreshold through a unit-sized (off) transistor. The second

type, gate leakage, is the current that leaks through the gate terminal. We determine the unit leakage current using

MASTAR [50]. In McPAT, the unit I

includes both the gate leakage current ﬂows through the channel to the gate and

the gate leakage current ﬂows through the source/drain and gate overlap.

In order to model the leakage current for a circuit block with many transistors, we need to consider which logical

state each transistor is in, then sum up the leakage current components for each. If a circuit block is in some logical

state s, we can express the effective width of all (off) transistors exhibiting subthreshold leakage in that state as W

sub

(s);

similarly, we can express the effective widths for gate leakage for on and off transistors as W

(s) and W

o f f

(s). If

Pr(s) is the probability that a circuit is in state s, we can express the total leakage current for a given block as the average

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