μPD160040：256灰度级TFT-LCD驱动器数据手册

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"uPD160040_20030101.pdf" 是一份关于μPD160040型号的384-输出TFT-LCD驱动器的数据手册，它适用于具有256灰度级别的显示屏。该文档发布于2003年1月，由NEC Electronics提供，用于确保用户使用的是最新版本。该驱动器的主要特性包括其数字化输入设计，采用8位数据乘以6个点（即每个像素2个点），能够通过内部D/A转换器实现256级灰度输出，这使得它可以驱动一个拥有16,777,216种颜色的全彩显示。这种设计的优势在于，由于驱动器的输出范围广泛，从VSS2加上0.2伏特到VDD2减去0.2伏特，因此在LCD的公共电极上进行水平、垂直线反转操作变得不必要，提高了显示的灵活性和效率。此外，μPD160040还支持处理点线反转（dot-line inversion）、N线反转（n-line inversion）以及列线反转（column line inversion），这些特性允许在高分辨率显示中实现精确的图像控制，适合于各种复杂图形的应用，如电子书阅读器、工业仪表、汽车仪表盘等。值得注意的是，这份文档强调了产品可能在全球不同地区不完全可用，因此在购买或使用前，建议咨询NEC Electronics的销售代表以获取产品在当地的具体供应情况和额外技术细节。同时，由于文档是在2001年修订并印刷，可能存在后续的技术更新或改进，用户应确认当前版本是否包含了所有最新的功能和优化。 μPD160040是一款高效且兼容性强的TFT-LCD驱动器，其独特的设计和高级功能使其在需要大量灰度控制和精细图像调整的场合具有竞争优势。对于从事相关电子产品设计或维护工作的工程师而言，理解和掌握这款驱动器的工作原理和使用方法是至关重要的。

Data Sheet S15859EJ1V0DS

µµ

PD160040

4. PIN FUNCTIONS

(1/2)

Pin Symbol Pin Name I/O Description

to S

384

Driver Output The D/A converted 256-gray-scale analog voltage is output.

to D

Port 1 display data Input The display data is input with a width of 48 bits, viz., the gray scale data

to D

(8 bits) by 6 dots (2 pixels).

to D

: LSB, D

: MSB

to D

Port 2 display data Input

to D

R,/L Shift direction control Input The shift direction control pin of shift register. The shift directions of the

shift registers are as follows.

R,/L = H (right shift): STHR input, S

→S

384

, STHL output

R,/L = L (left shift): STHL input, S

384

→S

, STHR output

STHR Right shift start pulse I/O

STHL Left shift start pulse I/O

These are the start pulse input/output pins when connected in cascade.

Loading of display data starts when a H level is read at the rising edge

of CLK.

A H level should be input at the pulse of one cycle of the clock signal.

If the start pulse input is more than 2 CLK, the first 1 CLK of the H-level

input is valid.

For right shift, STHR is input and STHL is output.

For left shift, STHL is input and STHR is output.

CLK Shift clock Input The shift clock input pin of shift register. The display data is loaded into

the data register at the rising edge.

When 66-clock pulses are input after input of the start pulse, input of

display data is halted automatically. The contents of the shift register

are cleared at the STB’s rising edge.

STB Latch Input The contents of the data register are transferred to the latch circuit at

the rising edge. In addition, at the falling edge, the gray scale voltage is

supplied to the driver. It is necessary to ensure input of one pulse per

horizontal period.

SRC Through rate control Input SRC = H: High-through-rate period (large current consumption)

SRC = L: Low-through-rate period (small current consumption)

SRC is pulled up to the V

DD1

in the IC.

ORC Output resistance control Input ORC = H: Low output resistance period

ORC = L: High output resistance period

ORC is pulled up to the V

DD1

in the IC.

POL Polarity input Input POL = L: The S

2n−1

output uses V

-V

as the reference supply. The S

output uses V

-V

as the reference supply.

POL = H: The S

2n−1

output uses V

-V

as the reference supply. The S

output uses V

-V

as the reference supply.

2n−1

indicates the odd output and S

indicates the even output. Input

of the POL signal is allowed the setup time (t

POL–STB

) with respect to

STB’s rising edge.

When it switches such as POL = H→L or L→H, all output pins are

output reset during STB = H. When it does not switch, all output pins

become Hi-Z (high impedance) during STB = H. Refer to 7.

RELATIONSHIP BETWEEN MODE, STB, SRC, ORC, POL, AND

OUTPUT WAVEFORM for details.

★

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