IEEE
Std
1149.5-1995
IEEE
STANDARD
FOR
MODULE
TEST
AND
c)
d)
e)
f)
g)
A positive logic convention
is
used for
all
figures
io
this
document, i.e.,
a
logic
1
value designates
the most positive of the
two
voltages
used
for signals, including the MTM-Bus clock signal, MCLK.
When a set
of
related bits are denoted by
a
common name, the bits within the set are identified by
number with the least significant bit numbered
0.
The identifier for a single bit in a series
of
related bits (e.g.,
a
packet) is the bit position number in
the
series enclosed in angle brackets
(“e”
and
‘5”).
The expression
<m..n>
is used
as
an
abbreviated identifier
for
a series
of
bits
m
to
n,
inclusive (e.g.,
the bits in a register or packet), where
m
and
n
are
the
most
and
least
significant bits, respectively.
The phrases “signal driver(s),” “signal output(s),” and “signal input@),” when implicitly or explic-
itly refemng to MTM-Bus signals, shall
be
taken to refer
to
one
or
more MTM-Bus signals
exclu-
sive
of
MCLK unless explicitly indicated otherwise.
M-module
is used as an abbreviation for
“MTM-Bus
Master module.”
S-module
is
used as an abbreviation for “MTM-Bus Slave module.”
In
all diagrams depicting registers, packets, and data fields within registers and packets, the most
significant bit (msb)
of
each depicted element
is
assumed to
be
left-most within the rectangle defin-
ing the data entity.
Any reference
to
a figure in
this
document is intended to reference
all
drawings and text in that fig-
ure.
h)
i)
j)
k)
2.3
Definitions
The following terms are used within
this
Stantiard. Clause, subclause, table, or figure numbers are given in
parentheses
to
indicate specific places in the text where
terms
are discussed
in
detail.
2.3.1
ACKNOWLEDGE
packet:
The first packet returned
by
an individually addressed S-module that con-
veys to the M-module that the appropriate S-module
is
responding and indicates the current status
of
the
responding S-module
(5.3).
2.3.2 active:
When associated with a logic level (e.g.,
in
the word “activc-low”),
this
term identifies the
logic level to which a signal shall
be
set to cause a defined action
io
occur. When referring to an output
driver (e.g., in the phrase “an active driver”),
this
term describes
the
mode in which the driver is capable
of
determining the voltage of the network
to
which it
is
connected
2.3.3 amnesia address:
The module address
(‘FA’
HEX)
to which a module will respond as though
uniquely addressed if that module
(1)
i~ii~~loiiimls
thc
abilily
lo
11~l;f~~t
wlioi
iI
ciilmot determine its address
unambiguously and
(2)
detects that it
c‘Iiiiio1
tkki
iiiiiic.
its
atltlrcsh
on;itr~higtioiisl~
(3.3).
2.3.4 application logic:
That portion of a module that excludes the
MTM-Bus
interface logic (figure
2-1).
2.3.5 assert:
To
change the value of a bus signal
from
logic
0
(released) to logic
1
(asserted) or ensure that
such a signal remains at a logic
1.
2.3.6 asserted:
Having a current value equal to logic
1
(said of
any
signal).
2.3.7
backplane:
Motherboard comprising
connectors
for
the
modules
of
a system and wiring interconnect-
ing
those modules. The intermodule wiring
of
the MTM-Bus is expected to
be
on this motherboard.
2.3.8
BMR:
Acronym for “broadcastlmulticast received.” See
2.3.10.
2.3.9 broadcast:
A mode
of
operation of the MTM-Bus in which
an
MTM-Bus Master transmits data to all
connected S-modules simultaneously throughout
a
message. Also, a message transmitted in this mode.
2-2
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