STM32U031系列：超低功耗与高性能的微控制器

需积分: 0 20 浏览量更新于2024-06-14 收藏 8.78MB PDF 举报

STM32U031系列是意法半导体（STMicroelectronics）推出的一款微控制器，它在功耗、性能和成本之间达到了良好的平衡。这个系列基于32位Arm Cortex-M0+核心，运行频率最高可达56 MHz，适用于对低功耗有严格要求的应用场景。STM32U031系列在节能方面表现出色，支持多种超低功耗模式，如VBAT模式、关断模式、待机模式、Stop2模式等，确保在不同工作状态下的极低电流消耗。 STM32U031X系列提供了不同配置，具有高达64 KB的Flash存储器和高达12 KB的SRAM，支持20至64引脚的多种封装形式，如TSSOP、WLCSP、UFQFPN、LQFP和UFBGA。这些器件包含了丰富的外设接口，如12位ADC、模拟比较器、运算放大器、低功耗RTC、通用和电机控制专用的定时器，以及多个I2C、SPI、USART和低功耗UART接口，便于在各种应用中实现灵活的通信。 STM32U031系列还包含了一些独特的特性，如批量采集模式（BAM），能够在Stop模式下快速唤醒，只需4微秒，这有助于减少能量损耗。此外，它还配备了Brownout Reset（BOR）功能，以防止电源电压过低导致的系统不稳定。在性能方面，STM32U031的Drystone2.1性能达到1.13 DMIPS/MHz，CoreMark分数为134，ULPMark-CP、ULPMark-PP和ULPMark-CM得分分别为377、153和20.3，表明其在低功耗计算上的高效性能。在内存方面，STM32U031拥有单银行Flash存储器，最大64 KB，并且具有代码读取保护功能，保证代码安全。12 KB的SRAM带有硬件奇偶校验检查，增强了数据稳定性。模拟外设包括12位ADC，转换速度快，可达0.4微秒，12位DAC输出通道以及低功耗采样保持功能。 STM32U031系列是针对低功耗应用而设计的微控制器，适用于需要长时间运行和高效能计算的物联网设备、传感器节点、便携式设备等。它的高性能、低功耗特性和丰富的外设集使得它在嵌入式系统设计中具有广泛的适用性。

• Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration

• Clock management: to reduce power consumption, the clock controller can stop the clock to the core,

individual peripherals or memory.

• System clock source: two different sources can deliver SYSCLK system clock:

– 4-48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE). It can supply clock

to system PLL. The HSE can also be configured in bypass mode for an external clock.

– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can supply clock to

system PLL.

– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 12 frequencies form

100 kHz to 48 MHz. When a 32.768 kHz clock source is available in the system (LSE), the MSI

frequency can be automatically trimmed by hardware to reach an accuracy better than ± 0.25%. The

MSI can supply a PLL.

– System PLL, which can be fed by HSE, HSI16 or MSI. It provides a system clock up to 56 MHz.

• Auxiliary clock source: three ultra-low-power clock sources for the real-time clock (RTC):

– 32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive capability modes.

The LSE can also be configured in bypass mode for using an external clock.

– 32 kHz low-speed internal RC oscillator (LSI) with ± 5% accuracy, also used to clock an independent

watchdog.

• Peripheral clock sources: several peripherals (RNG, USARTs, I2Cs, LPTIMs, ADC) have their own clock

independent of the system clock.

• Clock security system (CSS): in the event of HSE clock failure, the system clock is automatically

switched to HSI16 and, if enabled, a software interrupt is generated. LSE clock failure can also be detected

and generate an interrupt. The CSS feature can be enabled by software.

• Clock output:

– MCO (microcontroller clock output) provides one of the internal clocks for external use by the

application

– LSCO (low speed clock output) provides LSI or LSE in all low-power modes (except in VBAT

operation).

Several prescalers enable the application to configure AHB and APB domain clock frequencies, 56 MHz at

maximum.

3.10

General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without

pull-up or pull-down) or as peripheral alternate function (AF). Most of the GPIO pins are shared with special digital

or analog functions.

Through a specific sequence, this special function configuration of I/Os can be locked, such as to avoid spurious

writing to I/O control registers.

STM32U031x4/6/8

Functional overview

DS14581 - Rev 1

page 16/134

3.11 Direct memory access controller (DMA)

The direct memory access (DMA) controller is a bus master and system peripheral with single-AHB architecture.

With seven channels, it performs data transfers between memory-mapped peripherals and/or memories, to

offload the CPU.

Each channel is dedicated to managing memory access requests from one or more peripherals. The unit includes

an arbiter for handling the priority between DMA requests.

Main features of the DMA controller:

• Single-AHB master

• Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-to-peripheral data

transfers

• Access, as source and destination, to on-chip memory-mapped devices such as flash memory, SRAM, and

AHB and APB peripherals

• All DMA channels independently configurable:

– Each channel is associated either with a DMA request signal coming from a peripheral, or with a

software trigger in memory-to-memory transfers. This configuration is done by software.

– Priority between the requests is programmable by software (four levels per channel: very high, high,

medium, low) and by hardware in case of equality (such as request to channel 1 has priority over

request to channel 2).

– Transfer size of source and destination are independent (byte, half-word, word), emulating packing

and unpacking. Source and destination addresses must be aligned on the data size.

– Support of transfers from/to peripherals to/from memory with circular buffer management

– Programmable number of data to be transferred: 0 to 2

- 1

• Generation of an interrupt request per channel. Each interrupt request originates from any of the three

DMA events: transfer complete, half transfer, or transfer error.

3.12

DMA request multiplexer (DMAMUX)

The DMAMUX request multiplexer enables routing a DMA request line between the peripherals and the DMA

controller. Each channel selects a unique DMA request line, unconditionally or synchronously with events from its

DMAMUX synchronization inputs. DMAMUX may also be used as a DMA request generator from programmable

events on its input trigger signals.

3.13

Interrupts and events

The device flexibly manages events causing interrupts of linear program execution, called exceptions. The

Cortex

-M0+ processor core, a nested vectored interrupt controller (NVIC) and an extended interrupt/event

controller (EXTI) are the assets contributing to handling the exceptions. Exceptions include core-internal events

such as, for example, a division by zero and, core-external events such as logical level changes on physical lines.

Exceptions result in interrupting the program flow, executing an interrupt service routine (ISR) then resuming the

original program flow.

The processor context (contents of program pointer and status registers) is stacked upon program interrupt and

unstacked upon program resume, by hardware. This avoids context stacking and unstacking in the interrupt

service routines (ISRs) by software, thus saving time, code and power. The ability to abandon and restart load-

multiple and store-multiple operations significantly increases the device’s responsiveness in processing

exceptions.

3.13.1 Nested vectored interrupt controller (NVIC)

The configurable nested vectored interrupt controller is tightly coupled with the core. It handles physical line

events associated with a non-maskable interrupt (NMI) and maskable interrupts, and Cortex

-M0+ exceptions. It

provides flexible priority management.

The tight coupling of the processor core with NVIC significantly reduces the latency between interrupt events and

start of corresponding interrupt service routines (ISRs). The ISR vectors are listed in a vector table, stored in the

NVIC at a base address. The vector address of an ISR to execute is hardware-built from the vector table base

address and the ISR order number used as offset.

STM32U031x4/6/8

Functional overview

DS14581 - Rev 1

page 17/134

If a higher-priority interrupt event happens while a lower-priority interrupt event occurring just before is waiting for

being served, the later-arriving higher-priority interrupt event is served first. Another optimization is called tail-

chaining. Upon a return from a higher-priority ISR then start of a pending lower-priority ISR, the unnecessary

processor context unstacking and stacking is skipped. This reduces latency and contributes to power efficiency.

Features of the NVIC:

• Low-latency interrupt processing

• Four priority levels

• Handling of a non-maskable interrupt (NMI)

• Handling of 32 maskable interrupt lines

• Handling of 10 Cortex-M0+ exceptions

• Later-arriving higher-priority interrupt processed first

• Tail-chaining

• Interrupt vector retrieval by hardware

3.13.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller adds flexibility in handling physical line events and allows identifying

wake-up events at processor wake-up from Stop mode.

The EXTI controller has a number of channels, of which some with rising, falling or rising, and falling edge

detector capability. Any GPIO and a few peripheral signals can be connected to these channels.

The channels can be independently masked.

The EXTI controller can capture pulses shorter than the internal clock period.

A register in the EXTI controller latches every event even in Stop mode, which enables the software to identify the

origin of the processor wake-up from Stop mode or, to identify the GPIO and the edge event having caused an

interrupt.

3.14

Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator

polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the

scope of the EN/IEC 60335-1 standard, they offer a means of verifying the flash memory integrity. The CRC

calculation unit helps compute a signature of the software during runtime, to be compared with a reference

signature generated at link time and stored at a given memory location.

3.15

Analog-to-digital converter (ADC)

A native 12-bit analog-to-digital converter is embedded into STM32U031x4/6/8 devices. It can be extended to 16-

bit resolution through hardware oversampling. The ADC has up to 16 external channels and 3 internal channels

(temperature sensor, voltage reference, V

BAT

monitoring). It performs conversions in single-shot or scan mode. In

scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADC frequency is independent from the CPU frequency, allowing maximum sampling rate of ~2 Msps even

with a low CPU speed. An auto-shutdown function guarantees that the ADC is powered off except during the

active conversion phase.

The ADC can be served by the DMA controller. It can operate in the whole V

supply range.

The ADC features a hardware oversampler up to 256 samples, improving the resolution to 16 bits (refer to

AN2668).

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all scanned

channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start triggers,

to allow the application to synchronize A/D conversions with timers.

3.15.1 Temperature sensor

The temperature sensor (TS) generates a voltage V

that varies linearly with temperature.

The temperature sensor is internally connected to an ADC input to convert the sensor output voltage into a digital

value.

STM32U031x4/6/8

Functional overview

DS14581 - Rev 1

page 18/134

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature

measurement. As the offset of the temperature sensor may vary from part to part due to process variation, the

uncalibrated internal temperature sensor is suitable only for relative temperature measurements.

To improve the accuracy of the temperature sensor, each part is individually factory-calibrated by ST. The

resulting calibration data are stored in the part’s engineering bytes, accessible in read-only mode.

Table 5. Temperature sensor calibration values

Calibration value

name

Description Memory address

TS_CAL1

TS ADC raw data acquired at a temperature of 30 °C (± 5 °C),

DDA

= 3.0 V (± 10 mV)

0x1FFF 6E68 - 0x1FFF 6E69

TS_CAL2

TS ADC raw data acquired at a

temperature of 130 °C (± 5 °C),

DDA

= 3.0 V (± 10 mV)

0x1FFF 6E8A - 0x1FFF 6E8B

3.15.2 Internal voltage reference (V

REFINT

)

The internal voltage reference (V

REFINT

) provides a stable (bandgap) voltage output for the ADC and

comparators. V

REFINT

is internally connected to an ADC input. The V

REFINT

voltage is individually precisely

measured for each part by ST during production test and stored in the part’s engineering bytes. It is accessible in

read-only mode.

Table 6. Internal voltage reference calibration values

Calibration value

name

Description Memory address

REFINT

Raw data acquired at a temperature of 30 °C (± 5 °C),

DDA

= 3.0 V (± 10 mV)

0x1FFF 6EA4 - 0x1FFF 6EA5

3.15.3 V

BAT

battery voltage monitoring

This embedded hardware feature allows the application to measure the V

BAT

battery voltage using an internal

ADC input. As the V

BAT

voltage may be higher than V

DDA

and thus outside the ADC input range, the V

BAT

pin is

internally connected to a bridge divider by three. As a consequence, the converted digital value is one third the

BAT

voltage.

3.16

Digital-to-analog converter (DAC)

The single-channel 12-bit buffered DAC converts a digital value into an analog voltage available on the channel

output. The architecture of either channel is based on integrated resistor string and an inverting amplifier.

Features of the DAC:

• One DAC output channel

• 8-bit or 12-bit output mode

• Buffer offset calibration (factory and user trimming)

• Left or right data alignment in 12-bit mode

• Synchronized update capability

• Noise-wave generation

• Triangular-wave generation

• DMA capability

• Triggering with timer events, synchronized with DMA

• Triggering with external events

• Sample-and-hold low-power mode, with internal or external capacitor

STM32U031x4/6/8

Functional overview

DS14581 - Rev 1

page 19/134

3.17 Comparators (COMP)

STM32U031x4/6/8 embed an embedded rail-to-rail analog comparator with programmable reference voltage

(internal or external), hysteresis, speed (low for low-power), and output polarity.

The reference voltage can be one of the following:

• External, from an I/O

• Internal, from DAC

• Internal reference voltage (V

REFINT

) or its submultiple (1/4, 1/2, 3/4)

The comparators can wake up the device from Stop mode, generate interrupts, breaks or triggers for the timers

and can be also combined into a window comparator.

3.18 Operational amplifier (OPAMP)

The STM32U031x4/6/8 devices embed one operational amplifier with external and internal follower routing and

PGA capability.

Features of the operational amplifier:

• Low input bias current

• Low offset voltage

• Low-power mode

• Rail-to-rail input

3.19 True random-number generator (RNG)

The RNG is a true random number generator that provides full entropy outputs to the application as 32-bit

samples. It is composed of a live entropy source (analog) and an internal conditioning component.

3.20

Timers and watchdogs

The device includes an advanced-control timer, six general-purpose timers, two basic timers, two low-power

timers, two watchdog timers and a SysTick timer. Table 7 compares features of the advanced-control, general-

purpose and basic timers.

Table 7. Timer feature comparison

Timer type

Timer

Counter

resolution

Counter

type

Maximum

operating

frequency

Prescaler

factor

DMA

request

generation

Capture/

compare

channels

Compleme

ntary

outputs

Advanced-

control

TIM1 16-bit

Up, down,

up/down

56 MHz

Integer from

1 to 2

Yes 4 3

General

-purpose

TIM2 32-bit

Up, down,

up/down

56 MHz

Integer from

1 to 2

Yes 4 -

TIM3 16-bit

Up, down,

up/down

56 MHz

Integer from

1 to 2

Yes 4 -

TIM15 16-bit Up 56 MHz

Integer from

1 to 2

Yes 2 1

TIM16 16-bit Up 56 MHz

Integer from

1 to 2

Yes 1 1

Basic

TIM6 and

TIM7

16-bit Up 56 MHz

Integer from

1 to 2

Yes - -

Lower-

power

LPTIM1 and

LPTIM2

16-bit Up 56 MHz

where

n = 0 to 7

No N/A -

STM32U031x4/6/8

Functional overview

DS14581 - Rev 1

page 20/134

剩余133页未读，继续阅读

atonlink

粉丝: 101
资源: 7

STM32U031系列：超低功耗与高性能的微控制器

STM32U575xx超低功耗MCU数据手册：Arm Cortex-M33 + TrustZone + FPU

STM32F429官方数据手册：高性能Cortex-M4 MCU与丰富外设

STM8L101F3数据手册全面解读

STM32U575数据手册

STM32U073数据手册

STM32F103ZE中文数据手册

STM32F446数据手册

STM32F429数据手册

STM32U575 参考手册1

STM32F系列ARM内核32位微控制器数据手册

最新资源