FPGA视频协议开发技术在视频协议开发技术在LatticeECP3设计的应用设计的应用
Lattice公司的LatticeECP3 Versa评估板使设计者能评价和实验LatticeECP3现场可编门阵列,而LatticeECP3系
列可提供高性能的特性如增强DSP架构,高速SERDES和FPGA中高速源同步接口,这些特性使得LatticeECP3
系列非常适合用在量大高速低成本的产品如工业网络,工厂自动化,计算,医疗设备,国防和消费类电子。
Each LatticeECP3 device contains an array of logic blocks surrounded by Programmable I/O Cells
(PIC)。 Interspersed betwe
Lattice公司的LatticeECP3 Versa评估板使设计者能评价和实验LatticeECP3现场可编门阵列,而LatticeECP3系列可提供
高性能的特性如增强DSP架构,高速SERDES和FPGA中高速源同步接口,这些特性使得LatticeECP3系列非常适合用在量大
高速低成本的产品如工业网络,工厂自动化,计算,医疗设备,国防和消费类电子。
Each LatticeECP3 device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC)。
Interspersed between the rows of logic blocks are rows of sysMEM? Embedded Block RAM (EBR) and rows of sys-
DSP? Digital Signal Processing slices, as shown in Figure 2-1. The LatticeECP3-150 has four rows of DSP slices; all other
LatticeECP3 devices have two rows of DSP slices. In addition, the LatticeECP3 family contains SERDES Quads on the
bottom of the device. There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable
Functional Unit without RAM (PFF)。 The PFU contains the building blocks for logic, arithmetic, RAM and ROM
functions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks are
optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a
twodimensional array. Only one type of block is used per row. The LatticeECP3 devices contain one or more rows of
sysMEM EBR blocks. sysMEM EBRs are large, dedicated 18Kbit fast memory blocks. Each sysMEM block can be
configured in a variety of depths and widths as RAM or ROM. In addition, LatticeECP3 devices contain up to two rows of
DSP slices. Each DSP slice has multipliers and adder/accumulators, which are the building blocks for complex signal
processing capabilities. The LatticeECP3 devices feature up to 16 embedded 3.2Gbps SERDES (Serializer /
Deserializer) channels. Each SERDES channel contains independent 8b/10b encoding / decoding, polarity adjust and
elastic buffer logic. Each group of four SERDES channels, along with its Physical Coding Sub-layer (PCS) block, creates
a quad. The functionality of the SERDES/PCS quads can be controlled by memory cells set during device configuration or
by registers that are addressable during device operation. The registers in every quad can be programmed via the SERDES
Client Interface (SCI)。 These quads (up to four) are located at the bottom of the devices. Each PIC block
encompasses two PIOs (PIO pairs) with their respective sysI/O buffers. The sysI/O buffers of the LatticeECP3 devices
are arranged in seven banks, allowing the implementation of a wide variety of I/O standards. In addition, a separate I/O bank
is provided for the programming interfaces. 50% of the PIO pairs on the left and right edges of the device can be configured
as LVDS transmit/receive pairs. The PIC logic also includes pre-engineered support to aid in the implementation of high
speed source synchronous standards such as XGMII, 7:1 LVDS, along with memory interfaces including DDR3. Other
blocks provided include PLLs, DLLs and configuration functions. The LatticeECP3 architecture provides two Delay Locked
Loops (DLLs) and up to ten Phase Locked Loops (PLLs)。 The PLL and DLL blocks are located at the end of the
EBR/DSP rows. The configuration block that supports features such as configuration bit-stream decryption, transparent
updates and dual-boot support is located toward the center of this EBR row. Every device in the LatticeECP3 family
supports a sysCONFIG? port located in the corner between banks one and two, which allows for serial or parallel device
configuration. In addition, every device in the family has a JTAG port. This family also provides an on-chip oscillator and soft
error detect capability. The LatticeECP3 devices use 1.2V as their core voltage.
LatticeECP3主要特性:主要特性:
Higher Logic Density for Increased System Integration
17K to 149K LUTs
133 to 586 I/Os
Embedded SERDES
150 Mbps to 3.2 Gbps for Generic 8b10b, 10-bit SERDES, and 8-bit SERDES modes
Data Rates 230 Mbps to 3.2 Gbps per channel for all other protocols
Up to 16 channels per device: PCI Express, SONET/SDH, Ethernet (1GbE, SGMII, XAUI), CPRI, SMPTE 3G and
Serial RapidIO
sysDSP
Fully cascadable slice architecture
12 to 160 slices for high performance multiply and accumulate
Powerful 54-bit ALU operations