Micron LPDDR4 SDRAM详细特性与规格手册

5星 · 超过95%的资源需积分: 47 187 浏览量更新于2024-07-18 11 收藏 9.08MB PDF 举报

LPDDR4是一种高级动态随机访问存储器（DRAM）技术，特别适用于高性能、低功耗的应用场景，如汽车电子、移动设备等。本篇内容主要介绍了Micron公司生产的MT53B128M32型号的LPDDR4 SDRAM模块，其特性包括： 1. **电源管理**：该模块支持超低电压核心和I/O供电，VDD1工作电压范围为1.70-1.95V（典型值1.8V），而VDD2/VDDQ则为1.06-1.17V（典型值1.10V）。这种设计有助于降低功耗，提高能源效率。 2. **频率范围**：MT53B128M32支持从1866MHz到10MHz的频率，对应数据速率范围为3733-20Mb/s/pin，这使得它能适应不同的系统需求。 3. **架构与性能**：采用16级预取的DDR架构，每通道分为两部分，旨在减少读写操作的能量消耗和平均延迟。每个通道有8个内部银行，支持并行操作，提高数据传输速度。 4. **命令与数据传输**：单数据率CMD/ADR入口，以及每字节双向/差分数据 strobe，提供了灵活的数据传输方式。读写延迟（RL/WL）可编程，支持突发长度BL设定（16位或32位）。 5. **刷新功能**：通过定向每银行刷新，便于命令调度，并且可以实现并发银行操作。内置温度传感器用于控制自刷新速率，保证存储器在高温环境下的稳定工作。 6. **低功耗模式**：支持部分阵列自刷新（PASR）和可选的输出驱动强度（DS），以及时钟停止功能，进一步减小功耗。 7. **绿色设计**：产品符合RoHS标准，采用环保包装，体现出对可持续性的考量。 8. **标识选项**：提供两种电压选项，VDD1/VDD2为1.8V/1.1V，阵列配置为128M×32，即两个16M通道，每个通道由一个128M×32的单片die组成，封装形式为FBGA（球栅阵列）。 Micron MT53B128M32 LPDDR4 SDRAM是针对高效率和低功耗应用的理想选择，它的设计特点和功能组合使其能够在各种苛刻条件下保持卓越性能和稳定性。

Important Notes and Warnings

Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,

including without limitation specifications and product descriptions. This document supersedes and replaces all

information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-

ment if you obtain the product described herein from any unauthorized distributor or other source not authorized

by Micron.

Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi-

cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-

utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,

costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of

product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-

automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con-

ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron

products are not designed or intended for use in automotive applications unless specifically designated by Micron

as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in-

demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'

fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage

resulting from any use of non-automotive-grade products in automotive applications.

Critical Applications. Products are not authorized for use in applications in which failure of the Micron compo-

nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage

("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ-

mental damage by incorporating safety design measures into customer's applications to ensure that failure of the

Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron

component for any critical application, customer and distributor shall indemnify and hold harmless Micron and

its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,

costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of

product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi-

cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the

Micron product.

Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,

applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL-

URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE

WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR

PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included

in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en-

vironmental damages will result from failure of any semiconductor component.

Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential

damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,

breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly

authorized representative.

General Description

The 4Gb Mobile Low-Power DDR4 SDRAM (LPDDR4) is a high-speed CMOS, dynamic

random-access memory. The device is internally configured with 2 x16 channels, each

channel having 8-banks.

Micron Confidential and Proprietary

4Gb 200b: x32 Automotive LPDDR4 SDRAM

Important Notes and Warnings

CCMTD-1725822587-10406

200b_z00n_sdp_auto_lpddr4.pdf – Rev. E 5/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 3: Ball/Pad Descriptions

Symbol Type Description

CK_t_A, CK_c_A,

CK_t_B, CK_c_B

Input Clock: CK_t and CK_c are differential clock inputs. All address, command and control

input signals are sampled on positive edge of CK_t and the negative edge of CK_c. AC

timings for CA parameters are referenced to clock. Each channel (A, B) has its own

clock pair.

CKE0_A, CKE1_A,

CKE0_B, CKE1_B

Input Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock signals,

input buffers, and output drivers. Power-saving modes are entered and exited via CKE

transitions. CKE is sampled at the rising edge of CK.

CS0_A, CS1_A, CS0_B,

CS1_B

Input Chip select: Each channel (A, B) has its own CS signals.

CA[5:0]_A, CA[5:0]_B Input Command/Address inputs: Provide the command and address inputs according to

the command truth table. Each channel (A, B) has its own CA signals.

ODT_CA_A,

ODT_CA_B

Input CA ODT control: The ODT_CA pin is used in conjunction with the mode register to

turn on/off the on-die termination for CA pins. It is bonded to V

DD2

within the pack-

age, or at the package ball, for the terminating rank, and the non-terminating ranks

are bonded to V

(or left floating with a weak pull-down on the DRAM die). The ter-

minating rank is the DRAM that terminates the CA bus for all die on the same channel.

DQ[15:0]_A,

DQ[15:0]_B

I/O Data input/output: Bidirectional data bus.

DQS[1:0]_t_A,

DQS[1:0]_c_A,

DQS[1:0]_t_B,

DQS[1:0]_c_B

I/O Data strobe: DQS_t and DQS_c are bi-directional differential output clock signals

used to strobe data during a READ or WRITE. The data strobe is generated by the

DRAM for a READ and is edge-aligned with data. The data strobe is generated by the

SoC memory controller for a WRITE and is trained to precede data. Each byte of data

has a data strobe signal pair. Each channel (A, B) has its own DQS_t and DQS_c strobes.

DMI[1:0]_A,

DMI[1:0]_B

I/O Data mask/Data bus inversion: DMI is a dual use bi-directional signal used to indi-

cate data to be masked, and data which is inverted on the bus. For data bus inversion

(DBI), the DMI signal is driven HIGH when the data on the data bus is inverted, or driv-

en LOW when the data is in its normal state. DBI can be disabled via a mode register

setting. For data mask, the DMI signal is used in combination with the data lines to

indicate data to be masked in a MASK WRITE command (see the Data Mask (DM) and

Data Bus Inversion (DBI) sections for details). The data mask function can be disabled

via a mode register setting. Each byte of data has a DMI signal. Each channel has its

own DMI signals.

ZQ0, ZQ1 Reference ZQ calibration reference: Used to calibrate the output drive strength and the termi-

nation resistance. The ZQ pin shall be connected to V

DDQ

through a 240Ω ±1% resistor.

DDQ

, V

DD1

, V

DD2

Supply Power supplies: Isolated on the die for improved noise immunity.

Supply Ground reference: Power supply ground reference.

RESET_n Input RESET: When asserted LOW, the RESET pin resets all channels of the die.

DNU – Do not use: Must be grounded or left floating.

NC – No connect: Not internally connected.

Micron Confidential and Proprietary

4Gb 200b: x32 Automotive LPDDR4 SDRAM

Ball Assignments and Descriptions

CCMTD-1725822587-10406

200b_z00n_sdp_auto_lpddr4.pdf – Rev. E 5/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

剩余257页未读，继续阅读

cleve_mfr

粉丝: 5
资源: 11

Micron LPDDR4 SDRAM详细特性与规格手册

LPDDR4 LPDDR4X的上电时序及初始化--中文讲解.pdf

LPDDR3+LPDDR4+LPDDR5参数详解+学习

micron_lpddr4.pdf

LPDDR4_Spec.pdf

JESD209-4B(LPDDR4).pdf

LPDDR4_K4F2E3S4HM-MF(H)C_datasheet

RK_EVB_SOCBOARD_RK3399_LPDDR4P366SD8_V13_20170925.rar

D-00229 FORESEE_LPDDR4_FL4C2001G-D9_200ball_10x14.5x1.0_3200Mbps.pdf

LPDDR-3.pdf

LPDDR资料汇总.zip

最新资源