library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga_sync is
Port ( clk50_in : in std_logic;
Red_out : out std_logic;
Green_out : out std_logic;
Blue_out : out std_logic;
hs_out : out std_logic;
vs_out : out std_logic);
end vga_sync ;
architecture Behavioral of vga_sync is
signal Clk25 : std_logic;
signal Horizontal_Counter : std_logic_vector (9 downto 0);
signal Vertical_Counter : std_logic_vector (9 downto 0);
begin
--Generate 25Mhz Clock
process (clk50_in)
begin
if clk50_in'event and clk50_in='1' then
if (Clk25 = '0')then
Clk25 <= '1' after 2 ns;
else
Clk25 <= '0' after 2 ns;
end if;
end if;
end process;
process (Clk25)
TYPE Screen_Line1 is ARRAY(0 to 15, 0 to 47) OF std_logic;
CONSTANT char_L1 : Screen_Line1 :=(
('0','0','0','0','0','0','0','0','0','1','0','0','0','0','0','0','0','0','0','0','0','0','0','1','0','0','0','0','0','0','0','0','0','0','0','
0','0','0','0',
'0','0','0','0','0','0','0','0','0'),--1
('0','1','1','1','1','1','1','1','0','1','0','0','0','0','0','0','0','0','0','0','0','0','0','1','0','0','0','0','0','0','0','0','0','1','0','
0','0','1','1',
'1','1','1','1','1','1','0','0','0'),--2