CYUSB3014：高速USB3.0控制器集成与特性概览

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本文档介绍的是CYUSB3014芯片，一款由Cypress Semiconductor Corporation设计的高性能USB 3.0控制器。这款芯片支持USB 3.0和USB 2.0设备，并遵循USB 3.0规范版本1.0。它的主要特性包括： 1. **5-Gbps USB 3.0物理层（PHY）**: 符合PIPE 3.0标准，提供高达5 Gbps的数据传输速率，是USB 3.0技术的关键组成部分，提供了显著的速度提升。 2. **高速On-The-Go (HS-OTG)**: 支持HS-OTG模式，作为主机或外设时都能兼容USB OTG补充版本2.0，使得设备能够在多种角色间切换，增强其灵活性。 3. **32个物理端点**: 允许连接多个设备，提供丰富的连接选项，满足不同的应用需求。 4. **电池充电支持**: 符合USB Battery Charging Specification 1.1，支持对设备进行安全、高效的充电，以及检测外部附件充电器（ACA）的存在。 5. **通用可编程接口（GPIF™ II)**: 提供100 MHz的可编程接口，可以连接各种外部设备，支持8-、16-和32位数据总线，以及最多16个可配置控制信号，增强了与外部设备的交互能力。 6. **嵌入式32位CPU**: 配备ARM926EJ核心，运行速度达到200 MHz，拥有512 KB或256 KB嵌入式静态随机存取存储器(SRAM)，提供了强大的处理器性能。 7. **附加连接选项**: - I2C主控器：支持1 MHz的通信速率，可用于多种传感器和外围设备。 - I2C主控器（仅发送）：支持32 kHz、44.1 kHz和48 kHz的采样频率，适用于音频等需要精确定时的场合。 - UART支持：最大可达4 Mbps的串行通信，适用于远程数据传输。 - SPI主控器：支持33 MHz，便于控制存储器和其他SPI设备。 8. **可选时钟输入频率**: 提供灵活的时钟选择，以适应不同应用场景对频率的需求。 CYUSB3014是一款功能强大且兼容性高的USB 3.0控制器，广泛应用于需要高速数据传输、多设备连接和高级功能控制的设备中，如移动设备、消费电子和工业自动化系统。通过了解并利用这些特性，工程师们可以构建出具有竞争力的产品，满足现代电子设备的高速、智能和连接性要求。

CYUSB301X

Document Number: 001-52136 Rev. *L Page 7 of 40

JTAG Interface

FX3’s JTAG interface has a standard five-pin interface to connect

to a JTAG debugger in order to debug firmware through the

CPU-core's on-chip-debug circuitry.

Industry-standard debugging tools for the ARM926EJ-S core

can be used for the FX3 application development.

Other Interfaces

FX3 supports the following serial peripherals:

■ UART

■ I

■ SPI

The SPI, UART, and I

S interfaces are multiplexed on the serial

peripheral port.

The CYUSB3012 and CYUSB3014 Pin List (GPIF II with 32-bit

Data Bus Width) on page 13 shows details of how these inter-

faces are multiplexed. Note that when GPIF II is configured for a

32-bit data bus width (CYUSB3012 and CYUSB3014), only the

UART interface is available on GPIO[53] to GPIO[56].

UART Interface

The UART interface of FX3 supports full-duplex communication.

It includes the signals noted in Tabl e 1.

The UART is capable of generating a range of baud rates, from

300 bps to 4608 Kbps, selectable by the firmware. If flow control

is enabled, then FX3's UART only transmits data when the CTS

input is asserted. In addition to this, FX3's UART asserts the RTS

output signal, when it is ready to receive data.

C Interface

FX3’s I

C interface is compatible with the I

C Bus Specification

Revision 3. This I

C interface is capable of operating only as I

master; therefore, it may be used to communicate with other I

slave devices. For example, FX3 may boot from an EEPROM

connected to the I

C interface, as a selectable boot option.

FX3’s I

C Master Controller also supports multi-master mode

functionality.

The power supply for the I

C interface is VIO5, which is a

separate power domain from the other serial peripherals. This

gives the I

C interface the flexibility to operate at a different

voltage than the other serial interfaces.

The I

C controller supports bus frequencies of 100 kHz,

400 kHz, and 1 MHz. When VIO5 is 1.2 V, the maximum

operating frequency supported is 100 kHz. When VIO5 is 1.8 V,

2.5 V, or 3.3 V, the operating frequencies supported are 400 kHz

and 1 MHz. The I

C controller supports the clock-stretching

feature to enable slower devices to exercise flow control.

The I

C interface’s SCL and SDA signals require external pull-up

resistors. The pull-up resistors must be connected to VIO5.

S Interface

FX3 has an I

S port to support external audio codec devices.

FX3 functions as I

S Master as transmitter only. The I

S interface

consists of four signals: clock line (I2S_CLK), serial data line

(I2S_SD), word select line (I2S_WS), and master system clock

(I2S_MCLK). FX3 can generate the system clock as an output

on I2S_MCLK or accept an external system clock input on

I2S_MCLK.

The sampling frequencies supported by the I

S interface are

32 kHz, 44.1 kHz, and 48 kHz.

SPI Interface

FX3 supports an SPI Master interface on the Serial Peripherals

port. The maximum operation frequency is 33 MHz.

The SPI controller supports four modes

of SPI communication

(see SPI Timing Specification on page 32 for details on the

modes) with the Start-Stop clock. This controller is a

single-master controller with a single automated SSN control. It

supports transaction sizes ranging from 4 bits to 32 bits.

Table 1. UART Interface Signals

Signal Description

TX Output signal

RX Input signal

CTS Flow control

RTS Flow control

CYUSB301X

Document Number: 001-52136 Rev. *L Page 8 of 40

Boot Options

FX3 can load boot images from various sources, selected by the

configuration of the PMODE pins. Following are the FX3 boot

options:

■ Boot from USB

■ Boot from I

■ Boot from SPI (SPI devices supported are M25P16 (16 Mbit),

M25P80 (8 Mbit), and M25P40 (4 Mbit)) or their equivalents

■ Boot from GPIF II ASync ADMux mode

■ Boot from GPIF II Sync ADMux mode

■ Boot from GPIF II ASync SRAM mode

Reset

Hard Reset

A hard reset is initiated by asserting the Reset# pin on FX3. The

specific reset sequence and timing requirements are detailed in

Figure 18 on page 34 and Table 17 on page 33. All I/Os are

tristated during a hard reset.

Soft Reset

In a soft reset, the processor sets the appropriate bits in the

PP_INIT control register. There are two types of Soft Reset:

■ CPU Reset – The CPU Program Counter is reset. Firmware

does not need to be reloaded following a CPU Reset.

■ Whole Device Reset – This reset is identical to Hard Reset.

■ The firmware must be reloaded following a Whole Device

Reset.

Clocking

FX3 allows either a crystal to be connected between the XTALIN

and XTALOUT pins or an external clock to be connected at the

CLKIN pin. The XTALIN, XTALOUT, CLKIN, and CLKIN_32 pins

can be left unconnected if they are not used.

Crystal frequency supported is 19.2 MHz, while the external

clock frequencies supported are 19.2, 26, 38.4, and 52 MHz.

FX3 has an on-chip oscillator circuit that uses an external

19.2-MHz (±100 ppm) crystal (when the crystal option is used).

An appropriate load capacitance is required with a crystal. Refer

to the specification of the crystal used to determine the appro-

priate load capacitance. The FSLC[2:0] pins must be configured

appropriately to select the crystal- or clock-frequency option. The

configuration options are shown in Table 3.

Clock inputs to FX3 must meet the phase noise and jitter require-

ments specified in Table 4 on page 9.

The input clock frequency is independent of the clock and data

rate of the FX3 core or any of the device interfaces (including

P-Port and S-Port). The internal PLL applies the appropriate

clock multiply option depending on the input frequency.

Table 2. FX3 Booting Options

PMODE[2:0]

[2]

Boot From

F00 Sync ADMux (16-bit)

F01 Async ADMux (16-bit)

F11 USB boot

F0F Async SRAM (16-bit)

F1F I

C, On Failure, USB Boot is Enabled

1FF I

C only

0F1 SPI, On Failure, USB Boot is Enabled

Note

2. F indicates Floating.

Table 3. Crystal/Clock Frequency Selection

FSLC[2] FSLC[1] FSLC[0]

Crystal/Clock

Frequency

0 0 0 19.2-MHz crystal

1 0 0 19.2-MHz input CLK

1 0 1 26-MHz input CLK

1 1 0 38.4-MHz input CLK

1 1 1 52-MHz input CLK

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