TRF7963A: 13.56MHz RFID读写器IC for ISO/IEC14443A, B & NFC

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"TI-TRF7963A是一款由德州仪器(TI)推出的13.56MHz RFID读写器集成电路，适用于多种RFID和NFC标准，包括ISO/IEC14443A、ISO/IEC14443B和NFC论坛类型1至4及FeliCa™协议。该芯片集成了模拟前端(AFE)和数据成帧功能，以提供全面的解决方案。" TI-TRF7963A的关键特性包括： 1. **兼容性**：支持多种RFID和NFC标准，能够处理ISO/IEC14443A和B以及FeliCa™协议，这使得它在不同应用场景中具有广泛的适应性。 2. **供电范围**：输入电压可接受2.7VDC到5.5VDC，这种宽泛的电压范围使其能够在各种电源条件下工作。 3. **可编程输出功率**：可以设置为+20dBm（100mW）或+23dBm（200mW），提供灵活的功率控制，以满足不同距离的通信需求。 4. **I/O电压电平**：支持1.8VDC到5.5VDC的可编程I/O电压，适应不同接口设备的标准。 5. **系统时钟频率**：提供可编程的系统时钟输出，包括RF，RF/2，RF/4，这有助于优化系统的频率响应。 6. **调制深度**：可编程的调制深度允许用户根据具体应用调整通信质量。 7. **接收信号强度指示器（RSSI）**：双接收器架构带有RSSI功能，可以检测并防止读取漏洞，同时监测来自邻近读取器或环境中的噪声。 8. **低功耗模式**：支持多种功耗模式，包括关断模式，在关断状态下电流消耗低于0.5µA，非常适合超低功耗设计。 9. **接口灵活性**：提供并行和串行外设接口SPI，便于与各种微控制器连接。 10. **集成型电压稳压器**：内置电压稳压器为微控制器提供电源，简化了系统设计。 11. **工作温度范围**：能在-25°C到85°C的温度范围内正常工作，确保了在各种环境条件下的稳定性。 12. **封装形式**：采用32引脚QFN封装，尺寸为5mm x 5mm (RHB)，体积小巧，适合紧凑型应用。在应用方面，TI-TRF7963A主要用于： - **安全访问控制**：例如门禁系统，通过RFID技术实现安全的身份验证。 - **数字门锁**：利用RFID技术进行无钥匙开锁。 - **医疗系统**：如电子病历识别和药品追踪。 - **交通票务**：公交、地铁等公共交通的非接触式支付。 - **活动票务**：音乐会、体育赛事等的电子门票。 TRF7963A是设计高效、灵活的13.56MHz RFID读写器系统的理想选择，尤其适合对功耗、兼容性和可靠性有高要求的场合。

TRF7963A

ZHCS762F –DECEMBER 2011 –REVISED MAY 2017

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6.3 Supply Arrangements

Regulator Supply Input: VIN

The positive supply at VIN (pin 2) has an input voltage range of 2.7 V to 5.5 V. VIN provides the supply

input sources for three internal regulators with the output voltages VDD_RF, VDD_A, and VDD_X.

External bypass capacitors for supply noise filtering must be used (per reference schematics).

NOTE

VIN must be the highest voltage supplied to the TRF7963A.

RF Power Amplifier Regulator: VDD_RF

The VDD_RF (pin 3) regulator is supplying the RF power amplifier. The voltage regulator can be set for

either 5-V or 3-V operation. External bypass capacitors for supply noise filtering must be used (per

reference schematics). When configured for 5-V manual operation, the VDD_RF output voltage can be set

from 4.3 V to 5 V in 100-mV steps. In 3-V manual operation, the output can be programmed from 2.7 V to

3.4 V in 100-mV steps (see Table 6-2). The maximum output current capability for 5-V operation is 150

mA and for 3-V operation is 100 mA.

Analog Supply Regulator: VDD_A

Regulator VDD_A (pin 1) supplies the analog circuits of the device. The output voltage setting depends on

the input voltage and can be set for 5-V and 3-V operation. When configured for 5-V manual operation,

the output voltage is fixed at 3.4 V. External bypass capacitors for supply noise filtering must be used (per

reference schematics). When configured for 3-V manual operation, the VDD_A output can be set from 2.7

V to 3.4 V in 100-mV steps (see Table 6-2).

NOTE

The configuration of VDD_A and VDD_X regulators are not independent from each other.

The VDD_A output current should not exceed 20 mA.

Digital Supply Regulator: VDD_X

The digital supply regulator VDD_X (pin 32) provides the power for the internal digital building blocks and

can also be used to supply external electronics within the reader system. When configured for 3-V

operation, the output voltage can be set from 2.7 to 3.4 V in 100-mV steps. External bypass capacitors for

supply noise filtering must be used (refer to the reference schematics).

NOTE

The configuration of the VDD_A and VDD_X regulators are not independent from each other.

The VDD_X output current should not exceed 20 mA.

The RF power amplifier regulator (VDD_RF), analog supply regulator (VDD_A), and digital supply

regulator (VDD_X) can be configured to operate in either automatic or manual mode described in Table 6-

1. The automatic regulator setting mode ensures an optimal compromise between PSRR and the highest

possible supply voltage to ensure maximum RF power output.

By default, the regulators are set in automatic regulator setting mode. In this mode, the regulators are

automatically set every time the system is activated by setting EN input High or each time the automatic

regulator setting bit, B7 in register 0x0B is set to a 1. The action is started on the 0 to 1 transition. This

means that, if the user wants to rerun the automatic setting from a state in which the automatic setting bit

is already high, the automatic setting bit (B7 in register 0x0B) should be changed: 1-0-1.

TRF7963A

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By default, the regulator setting algorithm sets the regulator outputs to a "Delta Voltage" of 250 mV below

VIN, but not higher than 5 V for VDD_RF and 3.4 V for VDD_A and VDD_A. The "Delta Voltage" in

automatic regulator mode can be increased up to 400 mV (for more details, see bits B0 to B2 in register

0x0B).

Power Amplifier Supply: VDD_PA

The power amplifier of the TRF7963A is supplied through VDD_PA (pin 4). The positive supply pin for the

RF power amplifier is externally connected to the regulator output VDD_RF (pin 3).

I/O Level Shifter Supply: VDD_I/O

The TRF7963A has a separate supply input VDD_I/O (pin 16) for the build in I/O level shifter. The

supported input voltage ranges from 1.8 V to VIN, however not exceeding 5.5 V. Pin 16 is used to supply

the I/O interface pins (I/O_0 to I/O_7), IRQ, SYS_CLK, and DATA_CLK pins of the reader. In typical

applications, VDD_I/O is directly connected to VDD_X while VDD_X also supplies the MCU. This ensures

that the I/O signal levels of the MCU match with the logic levels of the TRF7963A.

Negative Supply Connections: VSS, VSS_RX, VSS_A, VSS_PA

The negative supply connections VSS_X of each functional block are all externally connected to GND.

The substrate connection is VSS (pin 10), the analog negative supply is VSS_A (pin 15), the logic

negative supply is VSS_D (pin 29), the RF output stage negative supply is VSS_PA (pin 6), and the

negative supply for the RF receiver VSS_RX (pin 7).

6.4 Supply Regulator Settings

The input supply voltage mode of the reader must be selected. This is done in the Chip Status Control

configuration is 5 V, which reflects an operating supply voltage range of 4.3 V to 5.5 V. If the supply

voltage is below 4.3 V, the 3-V configuration should be used.

The various regulators can be configured to operate in automatic or manual mode. This is done in the

Regulator and I/O Control register (0x0B) (see Table 6-1 and Table 6-2).

Table 6-1. Supply Regulator Setting: 5-V System

ADDRESS

OPTION BITS SETTING IN REGULATOR CONTROL

(1)

COMMENTS

B7 B6 B5 B4 B3 B2 B1 B0

Automatic Mode (default)

0B 1 x x x x x 1 1 Automatic regulator setting with 250-mV difference

0B 1 x x x x x 1 0 Automatic regulator setting with 350-mV difference

0B 1 x x x x x 0 0 Automatic regulator setting with 400-mV difference

Manual Mode

0B 0 x x x x 1 1 1 VDD_RF = 5 V, VDD_A = 3.4 V, VDD_X = 3.4 V

0B 0 x x x x 1 1 0 VDD_RF = 4.9 V, VDD_A = 3.4 V, VDD_X = 3.4 V

0B 0 x x x x 1 0 1 VDD_RF = 4.8 V, VDD_A = 3.4 V, VDD_X = 3.4 V

0B 0 x x x x 1 0 0 VDD_RF = 4.7 V, VDD_A = 3.4 V, VDD_X = 3.4 V

0B 0 x x x x 0 1 1 VDD_RF = 4.6 V, VDD_A = 3.4 V, VDD_X = 3.4 V

0B 0 x x x x 0 1 0 VDD_RF = 4.5 V, VDD_A = 3.4 V, VDD_X = 3.4 V

0B 0 x x x x 0 0 1 VDD_RF = 4.4 V, VDD_A = 3.4 V, VDD_X = 3.4 V

0B 0 x x x x 0 0 0 VDD_RF = 4.3 V, VDD_A = 3.4 V, VDD_X = 3.4 V

TRF7963A

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Table 6-2. Supply Regulator Setting: 3-V System

ADDRESS

OPTION BITS SETTING IN REGULATOR CONTROL

(1)

COMMENTS

B7 B6 B5 B4 B3 B2 B1 B0

Automatic Mode (default)

0B 1 x x x x x 1 1 Automatic regulator setting with 250-mV difference

0B 1 x x x x x 1 0 Automatic regulator setting with 350-mV difference

0B 1 x x x x x 0 0 Automatic regulator setting with 400-mV difference

Manual Mode

0B 0 x x x x 1 1 1 VDD_RF = 3.4 V, VDD_A = 3.4 V, VDD_X = 3.4 V

0B 0 x x x x 1 1 0 VDD_RF = 3.3 V, VDD_A = 3.3 V, VDD_X = 3.3 V

0B 0 x x x x 1 0 1 VDD_RF = 3.2 V, VDD_A = 3.2 V, VDD_X = 3.2 V

0B 0 x x x x 1 0 0 VDD_RF = 3.1 V, VDD_A = 3.1 V, VDD_X = 3.1 V

0B 0 x x x x 0 1 1 VDD_RF = 3.0 V, VDD_A = 3.0 V, VDD_X = 3.0 V

0B 0 x x x x 0 1 0 VDD_RF = 2.9 V, VDD_A = 2.9 V, VDD_X = 2.9 V

0B 0 x x x x 0 0 1 VDD_RF = 2.8 V, VDD_A = 2.8 V, VDD_X = 2.8 V

0B 0 x x x x 0 0 0 VDD_RF = 2.7 V, VDD_A = 2.7 V, VDD_X = 2.7 V

The regulator configuration function adjusts the regulator outputs by default to 250 mV below VIN level,

but not higher than 5 V for VDD_RF, 3.4 V for VDD_A and VDD_X. This ensures the highest possible

supply voltage for the RF output stage while maintaining an adequate PSRR (power supply rejection

ratio).

To further improve the PSRR, it is possible to increase the target voltage difference across VDD_X and

VDD_A from its default to 350 mV or even 400 mV (for details, see Regulator and I/O Control register

0x0B definition and Table 6-2.)

6.5 Power Modes

The chip has several power states, which are controlled by two input pins (EN and EN2) and several bits

in the Chip Status Control register (0x00).

Table 6-3 lists the configuration for the different power modes when using a 5-V or 3-V system supply.

The main reader enable signal is pin EN. When EN is set high, all of the reader regulators are enabled,

the 13.56-MHz oscillator is running, and the SYS_CLK (output clock for external microcontroller) is also

available.

The Regulator Control register settings shown are for optimized power out. The automatic setting

(normally 0x87) is optimized for best PSRR and noise reduction.

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