ZIC2410芯片技术规格与应用

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"ZIC2410是一款符合Zigbee规范和IEEE 802.15.4标准的单芯片解决方案，适用于各种无线应用，包括家庭自动化与安全、自动抄表、工厂自动化和电机控制、医疗患者监控、语音应用、传统有线UART的替代、能源管理以及遥控无钥匙进入系统等。该芯片集成了一颗兼容8051的微处理器，内置96KB闪存和8KB数据内存，支持250kbps至1Mbps的可扩展数据速率，以及μ-law/a-law/ADPCM语音编解码功能。其具有高射频接收灵敏度（-98dBm@1.5V）和高发射功率（+8dBm@1.5V），并提供4级电源管理模式，深度睡眠模式下的电流仅为0.3μA。ZIC2410可在1.9V至3.3V的单电压下工作，内部集成稳压器（1.5V核心电压）。为了便于定制应用的开发，还提供了软件工具和库支持。" ZIC2410芯片是一款高度集成的无线通信芯片，主要针对物联网(IoT)领域中的多种应用。它不仅符合Zigbee协议，还遵循了IEEE 802.15.4标准，这意味着它可以轻松地与其他Zigbee设备进行通信，构建低功耗、自组织的网络。在功能特性上，ZIC2410具有以下关键点： 1. **嵌入式8051兼容微处理器**：内含96KB的闪存用于存储程序，以及8KB的数据内存，为开发人员提供了足够的空间来编写和存储应用程序。 2. **可扩展的数据速率**：支持250kbps到1Mbps，适应不同应用场景对传输速度的需求，从低速的传感器网络到高速的数据传输都能应对。 3. **语音编码解码支持**：支持μ-law/a-law/ADPCM等标准，使ZIC2410在语音应用中表现出色，例如智能家居中的语音控制或医疗设备的远程监控。 4. **卓越的射频性能**：高接收灵敏度（-98dBm@1.5V）确保在弱信号环境下仍能稳定工作，而高发射功率（+8dBm@1.5V）则增强了通信距离。 5. **电源管理**：4级电源管理模式配合深度睡眠模式，使得ZIC2410在节能方面表现突出，适合电池供电或能量采集的IoT设备。 6. **单电压操作**：1.9V至3.3V的工作电压范围，加上内部的稳压器，简化了电源设计，降低了对外部元件的依赖。 7. **软件支持**：为开发人员提供完整的软件工具和库，有助于快速开发和调试自定义应用程序，降低了开发门槛。 ZIC2410芯片是实现各类物联网应用的理想选择，无论是在家庭自动化、工业控制，还是医疗监护等领域，都能发挥其强大的无线通信能力和高效能。结合其低功耗特性和易用的开发环境，ZIC2410为设计人员提供了一个高效的平台，以实现创新的无线解决方案。

ZIC2410 Datasheet

Bit Name Descriptions

Reset

R/W

Value

7:0

P3OEN

It controls the TX buffer function for each pin in Port3. When

each bit field is set to ‘0’, the TX buffer of the corresponding pin

outputs the value.

R/W 0x00

6:0

P1OEN

It controls the TX buffer function for each pin in Port1. When

each bit field is set to ‘0’, the TX buffer of the corresponding pin

outputs the value. P1.7 only acts as output.

R/W 0x00

7:0

P0OEN

It controls the TX buffer function for each pin in Port0. When

each bit field is set to ‘0’, the TX buffer of the corresponding pin

outputs the value.

R/W 0x00

P0REN/P1REN/P3REN (0xB9, 0xBA, 0xBC)

P0REN, P1REN, P3REN enable Pull-up of port 0, 1 and 3. When each bit area is cleared to ‘0’, the Pull-

up of the corresponding port is enabled.

7 Reserved 1

7:0

P3REN

It controls the Pull-up function for each pin in Port3. When each

bit field is set to ‘0’, the Pull-up function of the corresponding pin

is operated.

R/W 0xFF

6:0

P1REN

It controls the Pull-up function for each pin in Port1. When each

bit field is set to ‘0’, the Pull-up function of the corresponding pin

is operated.

*P1.7 doesn’t have a control field because it is operated as an

output.

R/W 0x7F

7:0

P0REN

It controls the Pull-up function for each pin in Port0. When each

bit field is set to ‘0’, the Pull-up function of the corresponding pin

is operated.

R/W 0xFF

P0MSK (P0 INPUT MASK REGISTER, 0x84)

7:0

P0MSK

This register is used for masking the input of P0 pin (Refer to

P0AndSel in P0SEL register).

R/W 0xFF

P0SEL (P0 INPUT SELECTION REGISTER, 0x85)

7:2 Reserved 0

ExNoEdge

Controls the wake up of the MCU by an external interrupt when in

the power-down mode.

When this field is ‘0’, the MCU wakes up when INT0 or INT1

signal is high (This is the normal case in the MCU.)

When this field is ‘1’, the MCU is woken up by the wakeup signal

of the SleepTimer. Remote control function can be implemented

by the interrupt service routine of the MCU when the WAKEUP

signal occurs by adjusting the RTDLY value in the Sleep Timer

while either INT0 or INT1 is low.

R/W 0

P0AndSel

When this field is set to ‘1’, P0 and P0MSK are ORed per bit. The

bits of the result value are to be ANed and then output to P1.7.

This function is used to implement remote control function.

R/W 0

Rev A Document No. 0005-05-07-00-000 Page 16 of 119

ZIC2410 Datasheet

1.5 INTERRUPTSCHEMES

The program interrupt functions of the embedded MCU are similar to other microprocessors.

When an interrupt occurs, the interrupt service routine at the corresponding vector address is

executed. When the interrupt service routine process is completed, the program is resumed

from the point of time at which the interrupt occurred. Interrupts can be initiated from the

internal operation of the embedded microprocessor (e.g. the overflow of the timer count) or from

an external signal.

The ZIC2410 has 13 interrupt sources. Table 6 describes the detailed information for each of

the interrupt sources. The ‘Interrupt Address’ indicates the address where the interrupt service

routine is located. The ‘Interrupt Flag’ is the bit that notifies the MCU that the corresponding

interrupt has occurred. ‘Interrupt Enable’ is the bit which decides whether each interrupt has

been enabled. ‘Interrupt Priority’ is the bit which decides the priority of the interrupt. The

‘Interrupt Number’ is the interrupt priority fixed by the hardware. That is, when two or more

interrupts having the same ‘Interrupt Priority’ value, occur simultaneously, the lower ‘Interrupt

Number’ is processed first.

Table 6 – Interrupt Descriptions

Interrupt

Number

Interrupt Type

Interrupt

Address

Interrupt Flag

Interrupt

Enable

Interrupt

Priority

0 External Interrupt0 0003H TCON.IE0 IE.EX0 IP.PX0

1 Timer0 Interrupt 000BH TCON.TF0 IE.ET0 IP.PT0

2 External Interrupt1 0013H TCON.IE1 IE.EX1 IP.PX1

3 Timer1 Interrupt 001BH TCON.TF1 IE.ET1 IP.PT1

UART0 Interrupt (TX)

UART0 Interrupt (RX)

0023H

Note 1

IE.ES0 IP.PS0

UART1Interrupt (TX)

UART1 Interrupt (RX)

003BH

Note 1

IE.ES1 IP.PS1

8 PHY Interrupt 0043H EXIF.PHYIF EIE.RFIE EIP.RFIP

9 Timer2 Interrupt 004BH EXIF.T2IF EIE.T2IE EIP.T2IP

10 AES Interrupt 0053H EXIF.AESIF EIE.AESIE EIP.AESIP

11 Timer3 Interrupt 005BH EXIF.T3IF EIE.T3IE EIP.T3IP

12 Sleep Timer Interrupt 0063H EICON.RTCIF EIE.RTCIE EIP.RTCIP

13 SPI Interrupt 0068H

Note 2

EIE.SPIIE EIP.SPIIP

14 Voice Interrupt 0073H

Note 3

EIE.VCEIE EIP.VCEIP

Note 1: In the case of a UART Interrupt, bit [0] of the IIR register (0x2502, 0x2512) in the UART block is used as a

flag. Also, the Tx, Rx, Timeout, Line Status and Modem Status interrupts can be distinguished by bit [3:1] value.

For more detailed information, refer to the UART0/1 description in Section 1.7.6.

Note 2: In the case of an SPI interrupt, there is another interrupt enable bit in the SPI register besides EIE.SPIIE.

In order to enable an SPI interrupt, both SPIE in the SPCR (0x2540) register and EIE.SPIIE should be set to ‘1.

SPIF in the SPSR (0x2541) register acts as an interrupt flag.

Note 3: In case of a Voice interrupt, there are interrupt enable registers and interrupt flag registers in the voice

block. The interrupt enable register are VTFINTENA (0x2770), VRFINTENA (0x2771) and VDMINTENA (0x2772).

The interrupt flag register are VTFINTVAL (0x2776), VRFINTVAL (0x2777), and VDMINTVAL (0x2778). There are

24 interrupt sources. When both an interrupt enable signal and an interrupt flag signal are set to ‘1,’ voice interrupt

is enabled.

Rev A Document No. 0005-05-07-00-000 Page 20 of 119

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