BCM6358：一体化ADSL2+ IAD处理器数据手册

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本资源是博通公司针对路由器解决方案的BCM6358处理器数据手册，该手册发布于2007年，专门针对高性能的ADSL2+集成接入设备（IAD）。BCM6358是一款单芯片设计，集成了先进的ADSL2+功能，旨在满足融合了语音、以太网和无线家庭网络的高级网关应用需求。核心亮点在于BCM6358采用的800DMIPS VIPER™（Voice-over-IP Enhanced RISC）处理器，这是一款专为ADSL2+应用定制的高效能处理器，它提供了卓越的集成度和性能，显著降低了系统成本，并消除了外部数字信号处理器（DSP）对于VoIP应用的需求。这款芯片还内置了一款支持全速率ADSL2+连接的调制解调器和AFE（Analog Front End），确保了符合国际标准，如ITU和ANSI。此外，BCM6358与博通的领先VDSL2调制解调器（BCM6314）配合使用，使其成为VDSL2桥接的理想主机CPU。这意味着它能够支持高速的VDSL2通信技术，进一步扩展了家庭网络的宽带能力。整体来说，BCM6358旨在通过其集成性和高效率，简化了家庭网络设备的设计，提升了用户体验，并在降低成本的同时提高了系统性能。手册详细介绍了芯片的架构图（Figure 1：BCM6358 Block Diagram），展示了其内部组件的功能划分和相互作用。对于那些从事路由器设计或寻求在ADSL2+和VDSL2技术上进行创新的工程师而言，这份数据手册提供了宝贵的参考材料，涵盖了硬件设计、软件接口、性能指标以及功耗管理等方面的信息，是构建下一代家庭网络设备的关键技术文档。

1/29/2007 7IAKO

BCM6358 Preliminary Data Sheet

01/26/07

Broadcom Corporation

Page xvi Document 6358-DS101-R

1/29/2007 7IAKO

Preliminary Data Sheet BCM6358

01/26/07

Broadcom Corporation

Document 6358-DS101-R Page xvii

LIST OF FIGURES

Figure 1: BCM6358 Block Diagram ......................................................................................................................i

Figure 2: BCM6358 High-Performance Single-Chip ADSL2+ IAD Block Diagram............................................. 1

Figure 3: ADSL PHY Block Diagram ................................................................................................................ 37

Figure 4: AFE Functional Block Diagram ......................................................................................................... 43

Figure 5: ATM SAR Processor Block Diagram................................................................................................. 45

Figure 6: Transmit Data Path Flow................................................................................................................... 47

Figure 7: Transmit DMA Controller................................................................................................................... 48

Figure 8: Transmit SDRAM Sub-channel Queue Structure.............................................................................. 49

Figure 9: Transmit SDRAM Queue Operation.................................................................................................. 50

Figure 10: AAL5 CPCS Operation.................................................................................................................... 53

Figure 11: Cell Header ..................................................................................................................................... 60

Figure 12: VPI/VCI/Port Table (VTBL) Entry Format........................................................................................ 61

Figure 13: Receive Data Flow .......................................................................................................................... 63

Figure 14: AAL5/0 CPCS.................................................................................................................................. 68

Figure 15: Receive DMA Controller Operation ................................................................................................. 70

Figure 16: Free Queues ................................................................................................................................... 71

Figure 17: Receive Queues.............................................................................................................................. 72

Figure 18: BCM6358 Processor Core Block Diagram ...................................................................................... 76

Figure 19: General Purpose Registers ............................................................................................................. 81

Figure 20: Special Registers ............................................................................................................................ 81

Figure 21: BCM6358 Memory Segments ....................................................................................................... 133

Figure 22: Virtual-to-Physical Translation....................................................................................................... 135

Figure 23: Address Translation with TLB ....................................................................................................... 137

Figure 24: TLB’s and TLB Registers .............................................................................................................. 138

Figure 25: Format of a TLB Entry ................................................................................................................... 138

Figure 26: Zero-Wait Async Read Timing Diagram........................................................................................ 152

Figure 27: Back-to-Back Zero-Wait Async Read Timing Diagram ................................................................. 152

Figure 28: One-Wait Async Read Timing Diagram ........................................................................................ 153

Figure 29: Zero-Wait Async Write Timing Diagram ........................................................................................ 153

Figure 30: Back-to-Back Zero-Wait Async Write Timing Diagram.................................................................. 154

Figure 31: One-Wait Async Read Timing Diagram ........................................................................................ 154

Figure 32: Synchronous Read Timing Diagram ............................................................................................. 155

1/29/2007 7IAKO

BCM6358 Preliminary Data Sheet

01/26/07

Broadcom Corporation

Page xviii Document 6358-DS101-R

Figure 33: Synchronous Write Timing Diagram ..............................................................................................155

Figure 34: MIPs PPL and DDR Clocking ........................................................................................................158

Figure 35: Deskew PLL...................................................................................................................................160

Figure 36: Peripheral Block Diagram ..............................................................................................................161

Figure 37: Descriptor Ring Illustration.............................................................................................................165

Figure 38: State RAM Layout..........................................................................................................................167

Figure 39: IEEE 802.3 Ethernet Frame Format ..............................................................................................170

Figure 40: Ethernet MAC ................................................................................................................................171

Figure 41: Transmit Timing Diagram ..............................................................................................................180

Figure 42: Receive Timing Diagram ...............................................................................................................181

Figure 43: MII Management Frame ................................................................................................................181

Figure 44: USB Controller Block Diagram ......................................................................................................218

Figure 45: Port Configuration Diagram ...........................................................................................................224

Figure 46: TDM Timing With No Data Sampling Offset ..................................................................................231

Figure 47: TDM Timing With Data Sampling Offset........................................................................................232

Figure 48: PCM 8-bit Timeslot Timing (Timeslot 0).........................................................................................234

Figure 49: PCM 8-bit Timeslot Timing (Timeslot 1).........................................................................................234

Figure 50: PCM 16-bit Timeslot Timing ..........................................................................................................235

Figure 51: DMA Operation ..............................................................................................................................238

Figure 52: Timing Relationships .....................................................................................................................241

Figure 53: SPI Block Connections for Two-Wire Devices ...............................................................................242

Figure 54: SPI Block Connections for One-Wire Devices ...............................................................................243

Figure 55: Full-Duplex Read/Write..................................................................................................................244

Figure 56: Half-Duplex Write...........................................................................................................................245

Figure 57: Half-Duplex Read ..........................................................................................................................245

Figure 58: SPIMsgData FIFO Before and After States for Example SPI Transfer..........................................247

Figure 59: Timing Diagram for Example SPI Transfer ....................................................................................248

Figure 60: SPI R/W Protocol of Serial Memory Devices.................................................................................248

Figure 61: External Components Required for Proper Oscillator Operation ...................................................254

Figure 62: Internal Voltage Regulator Supplies Connection ...........................................................................256

Figure 63: 1.2V Switching Regulator Circuit ...................................................................................................258

Figure 64: Zero-Wait Async Read Timing Diagram ........................................................................................263

Figure 65: One-Wait Async Read Timing Diagram .........................................................................................264

Figure 66: Zero-Wait Async Write Timing Diagram.........................................................................................264

Figure 67: One-Wait Async Write Timing Diagram .........................................................................................265

1/29/2007 7IAKO

Preliminary Data Sheet BCM6358

01/26/07

Broadcom Corporation

Document 6358-DS101-R Page xix

Figure 68: Synchronous Read Timing Diagram ............................................................................................. 266

Figure 69: EBI Synchronous Write Timing Diagram....................................................................................... 267

Figure 70: PCMCIA Read Timing ................................................................................................................... 268

Figure 71: PCMCIA Write Timing ................................................................................................................... 269

Figure 72: PCM Highway Interface Timing..................................................................................................... 270

Figure 73: SPI Master Interface Timing.......................................................................................................... 270

Figure 74: UTOPIA Interface Timing Diagram................................................................................................ 271

Figure 75: DDR SDRAM Read (without Auto Precharge) ..............................................................................273

Figure 76: DDR SDRAM Write (without Auto Precharge) .............................................................................. 274

Figure 77: MII Input Timing............................................................................................................................. 277

Figure 78: MII Output Timing.......................................................................................................................... 278

Figure 79: Management Interface Timing....................................................................................................... 278

Figure 80: Management Interface Timing (with Preamble Suppression On).................................................. 279

Figure 81: Clock Timing.................................................................................................................................. 279

Figure 82: Power-Up Sequence Timing Diagram........................................................................................... 280

Figure 83: BCM6358 400-Ball Fine Pitch BGA............................................................................................... 282

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