LMK04228: 双环路PLL时钟抖动清除器

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"TI-LMK04228是一款高性能的时钟抖动清除器，具备双环路PLL，特别适用于需要低噪声和高稳定性的系统。它符合JESD204B标准，能够提供超低的RMS抖动性能，以及多种可配置的时钟输出。该器件适合于各种应用场景，如数据转换器接口，FPGA，以及VCXO备份参考时钟等。" TI的LMK04228是一款专为满足高精度和低抖动需求设计的时钟发生器。这款设备的核心是其双环路PLLatinum™锁相环技术，这使得LMK04228能够在多个输出时钟上实现极低的RMS抖动，从而提高系统的整体性能和稳定性。 1. **JESD204B兼容性**： LMK04228遵循JEDEC JESD204B标准，这是一种高速串行接口标准，用于数据转换器（如ADC和DAC）与数字信号处理器或FPGA之间的通信。这种兼容性确保了数据传输的精确性和可靠性。 2. **超低RMS抖动**： LMK04228具备出色的噪声抑制能力，其RMS抖动低至156fs（12kHz至20MHz频段），245fs（100Hz至20MHz频段）。这意味着即便在高频操作下，也能保持时钟信号的纯净，这对于需要高精度的系统至关重要。 3. **多时钟输出**：设备可以提供多达14个差分器件时钟，其中PLL2可产生多达7个SYSREF时钟，最高时钟输出频率可达1.25GHz。这些时钟输出可以通过LVPECL、LVDS进行编程，以适应不同的系统需求。 4. **灵活的输出选项**： PLL1提供缓冲的VCXO或晶体输出，支持LVPECL、LVDS和2xLVCMOS可编程输出。这允许设计者根据具体应用选择最适合的时钟类型。 5. **冗余输入时钟**： LMK04228的PLL1支持多达3个冗余输入时钟，提高了系统容错能力和可靠性。在主时钟出现故障时，系统可以无缝切换到备用时钟源。 6. **VCXO备份**：除了作为系统主时钟源，LMK04228还可以作为VCXO（电压控制晶体振荡器）的备份参考时钟，确保即使在主参考时钟失效的情况下，系统时钟的连续性。 7. **应用领域**：由于其卓越的性能和灵活性，LMK04228广泛应用于需要精确时钟同步的领域，包括通信、数据中心、测试测量设备、航空航天和国防，以及任何依赖高精度时钟信号的系统。 TI的LMK04228是一款高性能、低抖动、高灵活性的时钟解决方案，对于需要精确时钟源的系统来说，是一个理想的组件。在设计过程中，应确保参考最新的英文版数据表以获取最准确的技术信息。

LMK04228

www.ti.com.cn

ZHCSK16A –OCTOBER 2017–REVISED JULY 2019

8 Parameter Measurement Information

8.1 Charge Pump Current Specification Definitions

I1 = Charge Pump Sink Current at V

CPout

= V

– ΔV

I2 = Charge Pump Sink Current at V

CPout

= V

I3 = Charge Pump Sink Current at V

CPout

= ΔV

I4 = Charge Pump Source Current at V

CPout

= V

– ΔV

I5 = Charge Pump Source Current at V

CPout

= V

I6 = Charge Pump Source Current at V

CPout

= ΔV

ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this device.

8.1.1 Charge Pump Output Current Magnitude Variation vs. Charge Pump Output Voltage

8.1.2 Charge Pump Sink Current vs. Charge Pump Output Source Current Mismatch

8.1.3 Charge Pump Output Current Magnitude Variation vs. Ambient Temperature

GND

= | V

- V

= 2· V

Definition V

Definition for Output

Non-Inverting Clock

Inverting Clock

2· V

GND

= | V

- V

= 2· V

Definition V

Definition for Input

Non-Inverting Clock

Inverting Clock

2· V

LMK04228

ZHCSK16A –OCTOBER 2017–REVISED JULY 2019

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8.2 Differential Voltage Measurement Terminology

The differential voltage of a differential signal can be described by two different definitions causing confusion

when reading data sheets or communicating with other engineers. This section will address the measurement

and description of a differential signal so that the reader will be able to understand and distinguish between the

two different definitions when used.

The first definition used to describe a differential signal is the absolute value of the voltage potential between the

inverting and noninverting signal. The symbol for this first measurement is typically V

or V

depending on if an

input or output voltage is being described.

The second definition used to describe a differential signal is to measure the potential of the noninverting signal

with respect to the inverting signal. The symbol for this second measurement is V

and is a calculated

parameter. Nowhere in the IC does this signal exist with respect to ground, it only exists in reference to its

differential pair. V

can be measured directly by oscilloscopes with floating references, otherwise this value can

be calculated as twice the value of V

as described in the first description.

Figure 2 illustrates the two different definitions side-by-side for inputs and Figure 3 illustrates the two different

definitions side-by-side for outputs. The V

and V

definitions show V

and V

DC levels that the noninverting

and inverting signals toggle between with respect to ground. V

input and output definitions show that if the

inverting signal is considered the voltage potential reference, the noninverting signal voltage potential is now

increasing and decreasing above and below the noninverting reference. Thus the peak-to-peak voltage of the

differential signal can be measured.

and V

are often defined as volts (V) and V

is often defined as volts peak-to-peak (V

Figure 2. Two Different Definitions for

Differential Input Signals

Figure 3. Two Different Definitions for

Differential Output Signals

Refer to application note AN-912 Common Data Transmission Parameters and their Definitions (SNLA036) for

more information.

LMK04228

www.ti.com.cn

ZHCSK16A –OCTOBER 2017–REVISED JULY 2019

9 Detailed Description

9.1 Overview

The LMK04228 is a highly flexible dual-PLL jitter cleaner and integrated VCO clock generator, providing up to 15

configurable outputs. The typical use case for LMK04228 is as a cascaded dual-loop jitter cleaner for JESD204B

systems. However traditional (non-JESD204B) systems are possible with use of the large SYSREF divider to

produce a low frequency. Device Clock outputs (DCLKoutX) provide configurable LVDS and LVPECL options,

while the OSCout output may be used to provide a buffered copy of a VCXO/Crystal signal in LVDS, LVPECL, or

LVCMOS formats.

The LMK04228 may be configured for single-loop mode by powering down unused blocks in PLL1.

9.1.1 Jitter Cleaning

The dual-loop PLL architecture of the LMK04228 provides the lowest jitter performance over a wide range of

output frequencies and phase noise integration bandwidths. The first stage PLL (PLL1) is driven by an external

reference clock and uses an external VCXO or tunable crystal to provide a frequency-accurate, low phase noise

reference clock for the second stage frequency multiplication PLL (PLL2).

PLL1 typically uses a narrow loop bandwidth (typically between 10 Hz to 200 Hz) to retain the frequency

accuracy of the reference clock input signal while at the same time suppressing the higher offset frequency

phase noise that the reference clock may have accumulated along its path or from other circuits. This cleaned

reference clock provides the reference input to PLL2.

The low phase noise reference provided to PLL2 allows PLL2 to operate with a wide loop bandwidth (typically

between 50 kHz to 200 kHz). The loop bandwidth for PLL2 is chosen to take advantage of the superior high

offset frequency phase noise profile of the internal VCO and the good low offset frequency phase noise of the

reference VCXO or tunable crystal.

Ultra-low jitter is achieved by allowing the phase noise of the external VCXO or crystal to dominate the final

output phase noise at low offset frequencies, and the phase noise of the internal VCO to dominate the final

output phase noise at high offset frequencies. This results in best overall phase noise and jitter performance.

9.1.2 JEDEC JESD204B Support

The LMK04228 provides support for JEDEC JESD204B. The LMK04228 will clock up to 7 JESD204B targets

using 7 device clocks (DCLKoutX) and 7 SYSREF clocks (SDCLKoutY). Each device clock is grouped with a

SYSREF clock.

It is also possible to reprogram SYSREF clocks to behave as extra device clocks for applications which have

non-JESD204B clock requirements.

9.1.3 Three PLL1 Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*, and CLKin2/CLKin2*)

The LMK04228 has up to three reference clock inputs for PLL1 (CLKin0, CLKin1, and CLKin2). The active clock

is chosen based on CLKin_SEL_MODE. Automatic or manual switching can occur between the inputs.

CLKin0, CLKin1, and CLKin2 each have their own PLL1 R dividers.

CLKin2 is shared for use as OSCout. To use as CLKin2, OSCout must be powered down. See VCO_MUX,

OSCout_FMT for more details.

Fast manual switching between reference clocks is possible with a external pins CLKin_SEL0 and CLKin_SEL1.

9.1.4 VCXO- and Crystal-Buffered Output

The LMK04228 provides OSCout, which by default is a buffered copy of the PLL1 feedback/PLL2 reference

input. This reference input is typically a low noise VCXO or crystal. When using a VCXO, this output can be used

to clock external devices such as microcontrollers, FPGAs, CPLDs, and so forth, before the LMK04228 is

programmed.

The OSCout buffer output type is programmable to LVDS, LVPECL, or LVCMOS.

Once PLL1 lock is established, the buffered output of VCXO/crystal has a deterministic phase relationship with

the CLKin input used as the PLL1 reference.

LMK04228

ZHCSK16A –OCTOBER 2017–REVISED JULY 2019

www.ti.com.cn

Overview (continued)

9.1.5 Frequency Holdover

The LMK04228 supports holdover operation to keep the clock outputs on frequency with minimum drift when the

reference is lost until a valid reference clock signal is re-established.

9.1.6 PLL2 Integrated Loop Filter Poles

The LMK04228 features programmable 3rd- and 4th-order loop filter poles for PLL2. These internal resistors and

capacitor values may be selected from a fixed range of values to achieve either a 3rd- or 4th-order loop filter

response. The integrated programmable resistors and capacitors complement larger external components

mounted near the chip.

These integrated components can be effectively disabled by programming the integrated resistors and capacitors

to their minimum values.

9.1.7 Internal VCOs

The LMK04228 has two internal VCOs, selected by VCO_MUX. The output of the selected VCO is routed to the

Clock Distribution Path. This same selection is also fed back to the PLL2 phase detector through a prescaler and

N-divider.

9.1.8 Clock Distribution

The LMK04228 features a total of 14 PLL2 clock outputs driven from the internal VCO.

All PLL2 clock outputs have programmable output types. They can be programmed to LVPECL or LVDS formats.

The total number of clock outputs the LMK04228 is able to distribute, including OSCout, is up to 15 differential

clocks.

The following sections discuss specific features of the clock distribution channels that allow the user to control

various aspects of the output clocks.

9.1.8.1 Device Clock Divider

Each device clock, DCLKoutX, has a single clock output divider. The divider supports a divide range of 1 to 32

(even and odd) with 50% output duty cycle using duty cycle correction mode. The output of this divider may also

be directed to SDCLKoutY, where Y = X + 1.

9.1.8.2 SYSREF Clock Divider

The SYSREF clocks, SDCLKoutY, all share a common divider. The divider supports a divide range of 8 to 8191

(even and odd).

9.1.8.3 Device Clock Delay

The device clocks include both a analog and digital delay for phase adjustment of the clock outputs.

The analog delay allows a nominal 25-ps step size and range from 0 to 575 ps of granular delay. Enabling the

device clock analog delay adds a nominal 500-ps delay in addition to the programmed value.

The digital delay allows an output to be delayed from 3.5 to 32 VCO cycles. The delay step can be as small as

half the period of the clock distribution path. For example, 2-GHz VCO frequency results in 250-ps tuning steps.

The digital delay value takes effect on the clock outputs after a SYNC event. Fixed digital delay allows all the

outputs to have a known phase relationship upon a SYNC event and is typically performed at start-up.

9.1.8.4 SYSREF Delay

The global SYSREF divider includes a digital delay block which allows a global phase shift with respect to the

other clocks.

Each local SYSREF clock output includes both an analog and additional local digital delay for unique phase

adjustment of each SYSREF clock.

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