XILINX XC3S100E Spartan3 FPGA技术详解

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"XILINX XC3S100E用户手册" XILINX的XC3S100E是一款属于Spartan-3E系列的现场可编程门阵列（FPGA），该手册提供了关于这款器件的全面介绍和技术细节。Spartan-3E系列是XILINX公司设计的低成本、高性能的FPGA产品，适用于各种嵌入式系统和数字信号处理应用。模块1：介绍和订购信息这部分内容涵盖XC3S100E的基本介绍，包括其主要特性、架构概述、封装标记以及订购信息。用户可以了解到器件的主要功能和性能指标，以及如何根据项目需求选择合适的器件版本和封装形式。模块2：功能描述深入介绍了XC3S100E的内部结构和功能单元： 1. 输入/输出块（IOBs）：IOBs是FPGA与外部世界交互的关键组件，手册中详细解释了IOB的概述以及SelectIO™信号标准，这是一种灵活的输入输出标准，支持多种不同的电气接口。 2. 可配置逻辑块（CLB）：CLB是FPGA的核心，由多个可编程逻辑单元组成，可以根据设计需求配置成各种逻辑门电路。 3. 块RAM：集成在芯片内的内存资源，可用于存储数据或实现高速缓冲。 4. 专用乘法器：提供硬件乘法功能，加速计算密集型任务。 5. 数字时钟管理器（DCM）：用于时钟频率合成、倍频、分频和相位调整，确保系统的时序正确。 6. 时钟网络：管理和分布整个芯片的时钟信号。 7. 配置：说明如何对器件进行编程和配置。 8. 功耗：讨论了Spartan-3E FPGA的功耗管理策略，这对于低功耗应用至关重要。 9. 生产步进：描述了不同生产批次的器件可能存在的微小差异。模块3：直流和开关特性这部分详细列出了XC3S100E的电气性能参数，包括： 1. 直流电气特性：包括绝对最大额定值、电源电压规格、推荐工作条件和直流特性，这些参数对于确保器件的稳定运行至关重要。 2. 开关特性：涉及I/O时序、SLICE时序、DCM时序、BlockRAM时序、乘法器时序以及配置和JTAG（联合测试行动组）时序。这些信息对于理解和优化设计的高速信号传输性能非常有用。通过这份用户手册，设计者能够全面理解XC3S100E FPGA的特性和操作方式，从而在设计过程中有效地利用其资源，满足项目的需求。无论是初学者还是经验丰富的工程师，这份手册都是一个宝贵的参考资料。

Functional Description

16 www.xilinx.com DS312-2 (v3.4) November 9, 2006

Product Specification

HSTL and SSTL inputs use the Reference Voltage (V

REF

) to

bias the input-switching threshold. Once a configuration

data file is loaded into the FPGA that calls for the I/Os of a

given bank to use HSTL/SSTL, a few specifically reserved

I/O pins on the same bank automatically convert to V

REF

inputs. For banks that do not contain HSTL or SSTL, V

REF

pins remain available for user I/Os or input pins.

Differential standards employ a pair of signals, one the

opposite polarity of the other. The noise canceling proper-

ties (for example, Common-Mode Rejection) of these stan-

dards permit exceptionally high data transfer rates. This

subsection introduces the differential signaling capabilities

of Spartan-3E devices.

Each device-package combination designates specific I/O

pairs specially optimized to support differential standards.

HSTL_III_18

- -

Input/

Output

Input Input 1.1 1.8

SSTL18_I

- -

Input/

Output

Input Input 0.9 0.9

SSTL2_I

- - -

Input/

Output

Input 1.25 1.25

Notes:

1. N/R - Not required for input operation.

Tabl e 6: Single-Ended IOSTANDARD Bank Compatibility (Continued)

Single-Ended

IOSTANDARD

CCO

Supply/Compatibility Input Requirements

1.2V 1.5V 1.8V 2.5V 3.3V V

REF

Board

Termination

Voltage (V

)

Tabl e 7: Differential IOSTANDARD Bank Compatibility

Differential

IOSTANDARD

CCO

Supply Input

Requirements:

REF

Differential Bank

Restriction

(1)

1.8V 2.5V 3.3V

LVDS_25 Input

Input,

On-chip Differential Termination,

Output

Input

REF

is not used

for these I/O

standards

Applies to

Outputs Only

RSDS_25 Input

Input,

On-chip Differential Termination,

Output

Input

Applies to

Outputs Only

MINI_LVDS_25 Input

Input,

On-chip Differential Termination,

Output

Input

Applies to

Outputs Only

LVPECL_25 Input Input Input

No Differential

Bank Restriction

(other I/O bank

restrictions might

apply)

BLVDS_25 Input

Input,

Output

Input

DIFF_HSTL_I_18

Input,

Output

Input Input

DIFF_HSTL_III_18

Input,

Output

Input Input

DIFF_SSTL18_I

Input,

Output

Input Input

DIFF_SSTL2_I Input

Input,

Output

Input

Notes:

1. Each bank can support any two of the following: LVDS_25 outputs, MINI_LVDS_25 outputs, RSDS_25 outputs.

Functional Description

DS312-2 (v3.4) November 9, 2006 www.xilinx.com 17

Product Specification

Differential pairs can be shown in the Pin and Area Con-

straints Editor (PACE) with the “Show Differential Pairs”

option. A unique L-number, part of the pin name, identifies

the line-pairs associated with each bank (see Pinout

Descriptions in Module 4). For each pair, the letters P and

N designate the true and inverted lines, respectively. For

example, the pin names IO_L43P_3 and IO_L43N_3 indi-

cate the true and inverted lines comprising the line pair L43

on Bank 3.

CCO

provides current to the outputs and additionally pow-

ers the On-Chip Differential Termination. V

CCO

must be

2.5V when using the On-Chip Differential Termination. The

REF

lines are not required for differential operation.

To further understand how to combine multiple IOSTAN-

DARDs within a bank, refer to IOBs Organized into Banks,

page 18.

On-Chip Differential Termination

Spartan-3E devices provide an on-chip ~120Ω differential

termination across the input differential receiver terminals.

The on-chip input differential termination in Spartan-3E

devices potentially eliminates the external 100Ω termination

resistor commonly found in differential receiver circuits. Dif-

ferential termination is used for LVDS, mini-LVDS, and

RSDS as applications permit.

On-chip Differential Termination is available in banks with

CCO

= 2.5V and is not supported on dedicated input pins.

Set the DIFF_TERM attribute to TRUE to enable Differential

Termination on a differential I/O pin pair.

The DIFF_TERM attribute uses the following syntax in the

UCF file:

INST <I/O_BUFFER_INSTANTIATION_NAME>

DIFF_TERM = “<TRUE/FALSE>”;

Pull-Up and Pull-Down Resistors

Pull-up and pull-down resistors inside each IOB optionally

force a floating I/O or Input-only pin to a determined state.

Pull-up and pull-down resistors are commonly applied to

unused I/Os, inputs, and three-state outputs, but can be

used on any I/O or Input-only pin. The pull-up resistor con-

nects an IOB to V

CCO

through a resistor. The resistance

value depends on the V

CCO

voltage (see DC and Switch-

ing Characteristics in Module 3 for the specifications). The

pull-down resistor similarly connects an IOB to ground with

a resistor. The PULLUP and PULLDOWN attributes and

library primitives turn on these optional resistors.

By default, PULLDOWN resistors terminate all unused I/O

and Input-only pins. Unused I/O and Input-only pins can

alternatively be set to PULLUP or FLOAT. To change the

unused I/O Pad setting, set the Bitstream Generator (Bit-

Gen) option UnusedPin to PULLUP, PULLDOWN, or

FLOAT. The UnusedPin option is accessed through the

Properties for Generate Programming File in ISE. See Bit-

stream Generator (BitGen) Options.

During configuration a Low logic level on the HSWAP pin

activates pull-up resistors on all I/O and Input-only pins not

actively used in the selected configuration mode.

Keeper Circuit

Each I/O has an optional keeper circuit (see Figure 12) that

keeps bus lines from floating when not being actively driven.

The KEEPER

circuit retains the last logic level on a line after

all drivers have been turned off. Apply the KEEPER

attribute or use the KEEPER library primitive to use the

KEEPER circuitry. Pull-up and pull-down resistors override

the KEEPER settings.

Slew Rate Control and Drive Strength

Each IOB has a slew-rate control that sets the output

switching edge-rate for LVCMOS and LVTTL outputs. The

SLEW attribute controls the slew rate and can either be set

to SLOW (default) or FAST.

Each LVCMOS and LVTTL output additionally supports up

to six different drive current strengths as shown in Ta bl e 8 .

To adjust the drive strength for each output, the DRIVE

attribute is set to the desired drive strength: 2, 4, 6, 8, 12,

and 16. Unless otherwise specified in the FPGA application,

the software default IOSTANDARD is LVCMOS25, SLOW

slew rate, and 12 mA output drive.

Figure 11: Differential Inputs and Outputs

100Ω

~120Ω

Spartan-3E

Differential Input

= 50Ω

Spartan-3E

Differential

Output

Spartan-3E

Differential Input

with On-Chip

Differential

Terminator

= 50Ω

Spartan-3E

Differential

Output

DS312-2_24_082605

Figure 12: Keeper Circuit

Weak Pull-up

Weak Pull-down

Input Path

Output Path

Keeper

DS312-2_25_022805

Functional Description

18 www.xilinx.com DS312-2 (v3.4) November 9, 2006

Product Specification

High output current drive strength and FAST output slew

rates generally result in fastest I/O performance. However,

these same settings generally also result in transmission

line effects on the printed circuit board (PCB) for all but the

shortest board traces. Each IOB has independent slew rate

and drive strength controls. Use the slowest slew rate and

lowest output drive current that meets the performance

requirements for the end application.

Likewise, due to lead inductance, a given package supports

a limited number of simultaneous switching outputs (SSOs)

when using fast, high-drive outputs. Only use fast,

high-drive outputs when required by the application.

IOBs Organized into Banks

The Spartan-3E architecture organizes IOBs into four I/O

banks as shown in Figure 13. Each bank maintains sepa-

rate V

CCO

and V

REF

supplies. The separate supplies allow

each bank to independently set V

CCO

. Similarly, the V

REF

supplies may be set for each bank. Refer to Tabl e 6 and

Tabl e 7 for V

CCO

and V

REF

requirements.

When working with Spartan-3E devices, most of the differ-

ential I/O standards are compatible and can be combined

within any given bank. Each bank can support any two of

the following differential standards: LVDS_25 outputs,

MINI_LVDS_25 outputs, and RSDS_25 outputs. As an

example, LVDS_25 outputs, RSDS_25 outputs, and any

other differential inputs while using on-chip differential ter-

mination are a valid combination. A combination not allowed

is a single bank with LVDS_25 outputs, RSDS_25 outputs,

and MINI_LVDS_25 outputs.

I/O Banking Rules

When assigning I/Os to banks, these V

CCO

rules must be

followed:

1. All V

CCO

pins on the FPGA must be connected even if a

bank is unused.

2. All V

CCO

lines associated within a bank must be set to

the same voltage level.

3. The V

CCO

levels used by all standards assigned to the

I/Os of any given bank must agree. The Xilinx

development software checks for this. Ta bl e 6 and

Tabl e 7 describe how different standards use the V

CCO

supply.

4. If a bank does not have any V

CCO

requirements,

connect V

CCO

to an available voltage, such as 2.5V or

3.3V. Some configuration modes might place additional

CCO

requirements. Refer to Configuration for more

information.

If any of the standards assigned to the Inputs of the bank

use V

REF

, then the following additional rules must be

observed:

1. All V

REF

pins must be connected within a bank.

2. All V

REF

lines associated with the bank must be set to

the same voltage level.

3. The V

REF

levels used by all standards assigned to the

Inputs of the bank must agree. The Xilinx development

software checks for this. Ta bl e 6 describes how different

standards use the V

REF

supply.

If V

REF

is not required to bias the input switching thresholds,

all associated V

REF

pins within the bank can be used as

user I/Os or input pins.

Package Footprint Compatibility

Sometimes, applications outgrow the logic capacity of a

specific Spartan-3E FPGA. Fortunately, the Spartan-3E

family is designed so that multiple part types are available in

pin-compatible package footprints, as described in Pinout

Descriptions in Module 4. In some cases, there are subtle

differences between devices available in the same footprint.

Tabl e 8: Programmable Output Drive Current

IOSTANDARD

Output Drive Current (mA)

2 4 6 8 12 16

LVTTL

999999

LVCMOS33 999999

LVCMOS25 99999 -

LVCMOS18

9999 - -

LVCMOS15

999 - - -

LVCMOS12

9 - - - - -

Figure 13: Spartan-3E I/O Banks (top view)

DS312-2_26_021205

Bank 0

Bank 2

Bank 3

Bank 1

Functional Description

DS312-2 (v3.4) November 9, 2006 www.xilinx.com 19

Product Specification

These differences are outlined for each package, such as

pins that are unconnected on one device but connected on

another in the same package or pins that are dedicated

inputs on one package but full I/O on another. When design-

ing the printed circuit board (PCB), plan for potential future

upgrades and package migration.

The Spartan-3E family is not pin-compatible with any previ-

ous Xilinx FPGA family.

Dedicated Inputs

Dedicated Inputs are IOBs used only as inputs. Pin names

designate a Dedicated Input if the name starts with IP, for

example, IP or IP_Lxxx_x. Dedicated inputs retain the full

functionality of the IOB for input functions with a single

exception for differential inputs (IP_Lxxx_x). For the differ-

ential Dedicated Inputs, the on-chip differential termination

is not available. To replace the on-chip differential termina-

tion, choose a differential pair that supports outputs

(IO_Lxxx_x) or use an external 100Ω termination resistor on

the board.

ESD Protection

Clamp diodes protect all device pads against damage from

Electro-Static Discharge (ESD) as well as excessive voltage

transients. Each I/O has two clamp diodes: one diode

extends P-to-N from the pad to V

CCO

and a second diode

extends N-to-P from the pad to GND. During operation,

these diodes are normally biased in the off state. These

clamp diodes are always connected to the pad, regardless

of the signal standard selected. The presence of diodes lim-

its the ability of Spartan-3E I/Os to tolerate high signal volt-

ages. The V

absolute maximum rating in Tabl e 7 2 of DC

and Switching Characteristics (Module 3) specifies the

voltage range that I/Os can tolerate.

Supply Voltages for the IOBs

The IOBs are powered by three supplies:

1. The V

CCO

supplies, one for each of the FPGA’s I/O

banks, power the output drivers. The voltage on the

CCO

pins determines the voltage swing of the output

signal.

2. V

CCINT

is the main power supply for the FPGA’s internal

logic.

3. V

CCAUX

is an auxiliary source of power, primarily to

optimize the performance of various FPGA functions

such as I/O switching.

I/O and Input-Only Pin Behavior During

Power-On, Configuration, and User Mode

In this section, all behavior described for I/O pins also

applies to input-only pins and dual-purpose I/O pins that are

not actively involved in the currently-selected configuration

mode.

All I/O pins have ESD clamp diodes to their respective V

CCO

supply and from GND, as shown in Figure 5. The V

CCINT

(1.2V), V

CCAUX

(2.5V), and V

CCO

supplies can be applied in

any order. Before the FPGA can start its configuration pro-

cess, V

CCINT

, V

CCO

Bank 2, and V

CCAUX

must have reached

their respective minimum recommended operating levels

indicated in Tabl e 7 3 . At this time, all output drivers are in a

high-impedance state. V

CCO

Bank 2, V

CCINT

, and V

CCAUX

serve as inputs to the internal Power-On Reset circuit

(POR).

A Low level applied to the HSWAP input enables pull-up

resistors on user-I/O and input-only pins from power-on

throughout configuration. A High level on HSWAP disables

the pull-up resistors, allowing the I/Os to float. HSWAP con-

tains a weak pull-up and defaults to High if left floating. As

soon as power is applied, the FPGA begins initializing its

configuration memory. At the same time, the FPGA inter-

nally asserts the Global Set-Reset (GSR), which asynchro-

nously resets all IOB storage elements to a default Low

state. Also see Pin Behavior During Configuration.

Upon the completion of initialization and the beginning of

configuration, INIT_B goes High, sampling the M0, M1, and

M2 inputs to determine the configuration mode. Configura-

tion data is then loaded into the FPGA. The I/O drivers

remain in a high-impedance state (with or without pull-up

resistors, as determined by the HSWAP input) throughout

configuration.

At the end of configuration, the GSR net is released, placing

the IOB registers in a Low state by default, unless the

loaded design reverses the polarity of their respective SR

inputs.

The Global Three State (GTS) net is released during

Start-Up, marking the end of configuration and the begin-

ning of design operation in the User mode. After the GTS

net is released, all user I/Os go active while all unused I/Os

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