"TI-DS90CF386 FPD-Link接收器及LVDS数据传输"

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DS90CF366

DS90CF386

SNLS055J –NOVEMBER 1999–REVISED MAY 2016

www.ti.com

Product Folder Links: DS90CF366 DS90CF386

(1) Typical values are given for V

= 3.3 V and T

= 25°C.

(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground

unless otherwise specified (except V

and ΔV

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

(1)

MAX UNIT

LVCMOS DC SPECIFICATIONS

High level input voltage 2 V

Low level input voltage GND 0.8 V

High level output voltage I

= –0.4 mA 2.7 3.3 V

Low level output voltage I

= 2 mA 0.06 0.3 V

Input clamp voltage I

= –18 mA –0.79 –1.5 V

Input current

= 0.4 V, 2.5 V or V

1.8 15 uA

= GND –10 0 uA

Output short circuit current V

OUT

= 0 V –60 –120 mA

LVDS RECEIVER DC SPECIFICATIONS

Differential input high threshold V

= 1.2 V 100 mV

Differential input low threshold –100 mV

Input current

= 2.4 V, V

= 3.6 V ±10 μA

= 0 V, V

= 3.6 V ±10 μA

RECEIVER SUPPLY CURRENT

ICCRW

Receiver supply current

worst case

= 8 pF, worst case pattern,

DS90CF386, see Figure 1 and

Figure 4

f = 32.5 MHz 49 70 mA

f = 37.5 MHz 53 75 mA

f = 65 MHz 81 114 mA

f = 85 MHz 96 135 mA

= 8 pF, worst case pattern,

DS90CF366, see Figure 1 and

Figure 4

f = 32.5 MHz 49 60 mA

f = 37.5 MHz 53 65 mA

f = 65 MHz 78 100 mA

f = 85 MHz 90 115 mA

ICCRG

Receiver supply current,

16 grayscale

= 8 pF, 16 grayscale pattern,

see Figure 2, Figure 3, and

Figure 4

f = 32.5 MHz 28 45 mA

f = 37.5 MHz 30 47 mA

f = 65 MHz 43 60 mA

f = 85 MHz 43 70 mA

ICCRZ

Receiver supply current

power down

(2)

Power Down = low receiver outputs stay low during

power down mode

140 400 μA

DS90CF366

DS90CF386

www.ti.com

SNLS055J –NOVEMBER 1999–REVISED MAY 2016

Product Folder Links: DS90CF366 DS90CF386

(1) Typical values are given for V

= 3.3 V and T

= 25°C.

(2) Receiver skew margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter

pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows

for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less than 150 ps).

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

(1)

MAX UNIT

CLHT CMOS or LVCMOS low-to-high transition time See Figure 4 2 3.5 ns

CHLT CMOS or LVCMOS high-to-low transition time See Figure 4 1.8 3.5 ns

RSPos0 Receiver input strobe position for bit 0

f = 85 MHz, see Figure 11 and

Figure 12

0.49 0.84 1.19 ns

RSPos1 Receiver input strobe position for bit 1 f = 85 MHz 2.17 2.52 2.87 ns

RSPos2 Receiver input strobe position for bit 2 f = 85 MHz 3.85 4.2 4.55 ns

RSPos3 Receiver input strobe position for bit 3 f = 85 MHz 5.53 5.88 6.23 ns

RSPos4 Receiver input strobe position for bit 4 f = 85 MHz 7.21 7.56 7.91 ns

RSPos5 Receiver input strobe position for bit 5 f = 85 MHz 8.89 9.24 9.59 ns

RSPos6 Receiver input strobe position for bit 6 f = 85 MHz 10.57 10.92 11.27 ns

RSKM RxIN skew margin

(2)

f = 85 MHz, see Figure 13 290 ps

RCOP RxCLK OUT period See Figure 5 11.76 T 50 ns

RCOH RxCLK OUT high time f = 85 MHz, see Figure 5 4.5 5 7 ns

RCOL RxCLK OUT low time f = 85 MHz, see Figure 5 4 5 6.5 ns

RSRC RxOUT setup to RxCLK OUT f = 85 MHz, see Figure 5 2 ns

RHRC RxOUT hold to RxCLK OUT f = 85 MHz, see Figure 5 3.5 ns

RCCD RxCLK IN to RxCLK OUT delay 25°C, V

= 3.3 V, see Figure 6 5.5 7 9.5 ns

RPLLS Receiver phase lock loop set See Figure 7 10 ms

RPDD Receiver power down delay See Figure 10 1 μs

6.7 Timing Diagrams

Figure 1. Test Pattern, Worst Case

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