使用SystemVerilog的VMM简介：设计验证快速入门

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"虚拟化内存管理模型(Virtual Memory Management Model)介绍" 在电子设计自动化(Electronic Design Automation, EDA)领域，SystemVerilog Verification Methodology Manual (VMM) 是一种广泛使用的验证方法学，尤其在系统级验证和硬件设计中扮演着重要角色。SystemVerilog VMM 提供了一种框架，帮助工程师更有效地进行复杂集成电路的设计验证。 VMM（Verification Methodology Manual）是Synopsys公司推出的一种基于SystemVerilog语言的验证方法学，旨在提高设计验证的效率和质量。SystemVerilog是IEEE 1800标准定义的一种硬件描述语言，它不仅支持行为描述，还包含了丰富的验证组件和类库，使得编写高级验证环境成为可能。本快速入门指南《VMM: Introduction to Design Verification, A Quickstart Guide》版本1.0，旨在帮助读者快速掌握VMM的基本概念和应用。这份文档由Synopsys公司在2007和2008年发布，共计81页，涵盖了VMM的核心概念、架构以及如何在实际项目中运用VMM进行设计验证。 VMM的核心组件包括虚拟总线(Virtual Bus)、环境(Environment)、代理(Agents)、驱动(Drivers)、监视器(Monitors)、断言(Assertions)和覆盖(Coverage)等。虚拟总线允许不同模块之间的通信，环境则封装了验证逻辑，代理负责与被验证设计交互，驱动模拟外部激励，监视器记录设计的行为，断言确保设计满足功能规范，覆盖则用来评估验证的完整性。在使用VMM时，工程师可以构建可重用的验证组件，这些组件能够适应不同的设计需求，降低了验证工作的重复性劳动。此外，VMM还强调了模块化和层次化的验证方法，使得验证团队能够更有效地协同工作，提高整个项目的验证效率。尽管VMM主要由Synopsys推广，但它与其它EDA工具供应商的解决方案兼容，如 Mentor Graphics的OVM（Open Verification Methodology）和 Cadence的UVM（Universal Verification Methodology）。随着UVM的标准化（作为IEEE 1800-2012的一部分），许多VMM的概念和实践也已被UVM所采纳，这进一步证明了VMM在验证方法学中的影响力和实用性。 SystemVerilog VMM是设计验证领域的一个重要工具，它提供了强大的框架和类库，帮助工程师构建高效、可扩展的验证环境，从而确保集成电路设计的正确性和可靠性。通过深入理解和应用VMM，电子设计者可以提高他们的验证工作质量和效率，降低设计风险，最终加速产品上市的时间。

VMM: Introduction to Design Verification, A Quickstart Guide Version 1.0

Let‘s start by considering a very trivial example showing the usage of the base class

vmm_data. The data transactions are extended from vmm_data class.

First we declare a class called pkt_trans which is a transaction descriptor class, and

describes exactly what data we need to send through our system.

Let‘s assume our packet data consists of two different pieces of information: a 4-bit

number ―pen‖ and an enumerated type that describes the color. The color can be one of

6 colors described below.

Within the class pkt_trans , we have four properties, and four methods.

The first property is log which is an instance of the VMM logging base class, vmm_log

and is used to customize formatting of and filtering the messages coming from this class.

The next two properties are specific data information (pen and color). The last property

is a constraint named ―vanilla‖ which specifies that the value of ―pen‖ should be less

than 8.

The first method is the constructor for the object; all we need here is a call to its parent

class constructor new method (this is a requirement of Object Oriented features in

SystemVerilog).

The second method is the display method that is customized for this specific descriptor

class.

There is also vmm_data::allocate() method which is used in conjunction with factory

pattern usage, discussed in later sections. In this method a new instance of the data

transaction is created.

The next two methods are for the purpose of copying the data from one object descriptor

to another. The only custom parts of these methods are these two lines:

cpy.pen = this.pen;

cpy.color = this.color;

These are done after a call to the base class copy_data() method which takes care of all

the base member copying. The copy method creates a duplicate of the main transaction

object which is then sent through channels to appropriate transactors. Often when a

transaction is generated by means of VMM generic transaction generator or user defined

one would need to modify some parameters and send the transaction object but keep the

original transaction for checking purposes.

Here is a look at some member properties and methods of vmm_data base class. The

virtual functions and methods in the base class would be defined to perform the required

tasks based on the functionality that the extended classes would have

VMM: Introduction to Design Verification, A Quickstart Guide Version 1.0

tr2 = new();

tr.copy(tr2);

`vmm_note(tr2.log,(tr2.psdisplay("Copy of Random Descriptor") ));

$finish;

end

endprogram : test

Once we define a data transaction class (pkt_trans) and declare a variable of that type

(tr and tr2) we need to instantiate those objects before they are used. This process uses

a call to the constructor, new() method to actually create storage for the data transaction

object. Once the object is allocated we can call the built-in randomization routines.

In order to print the content of the object we use `vmm_note macro for message log class,

which prints out the header information as well as the customize version of its contents.

The output looks like:

Normal[NOTE] on PKT_TRANS(PKT_TRANS) at 0:

New Random Descriptor : [ 1:PINK]

Normal[NOTE] on PKT_TRANS(PKT_TRANS) at 0:

Copy of Random Descriptor : [ 1:PINK]

Communication means: Channels vmm_channel

The channel is used to exchange transactions between its components within the layers of

the testbench structure. For example, transactions can flow from the main generator to

the driver or from a monitor to the checker and scoreboard. The channels are one of

several mechanisms to move the data. The connection between these components is the

vmm_channel. One side produces the transaction, places the transactions into the

channel. The other side which consumes, retrieves the transactions out of the channel,

and acts upon them.

Although a SystemVerilog mailbox which acts as a FIFO is used as a common

connection mechanism for many designs, the vmm_channel has several advantages over

it, and uses a dynamic queue construct. The vmm_channel reduces coding errors since it

will automatically allow type-checking. The flow control mechanism is universal and

does allow for blocking and non-blocking as well as peeking and gathering information

on the content of the channel. It provides for level marking as well to allow more checks

and replication.

Macro for creating vmm_channel objects: ‘vmm_channel

The channel can be simply created using the ‘vmm_channel macro with the appropriate

data transaction as its argument. The data transaction is extended from vmm_data. Once

the data transaction is defined as a class extension of vmm_data then it can be used as an

argument for ‘vmm_channel. This macro will create channel objects for the data

transaction type.

For example, for the pkt_trans transaction, executing the following statement

`vmm_channel(pkt_trans)

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