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"原版英文UART和APB2UART协议文档全面解析"

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The original English documentation for the UART protocol, both the official version and the APB2UART protocol are the subject of discussion in this summary. It is noted that the availability of the official English version of these documents is limited online, with many translations into Chinese being the only versions available. The document copyright dates are specified as 2000, 2001, 2005, and 2007, with all rights reserved by ARM Limited. The specific reference is ARM DDI 0183G for the PrimeCell® UART (PL011), with a revision of r1p5. The technical reference manual for the PrimeCell UART (PL011) is also covered under the same copyright and rights reservation notice. The release information for the manual is detailed in a change history table, which outlines the modifications made to the document. Additionally, a proprietary notice is included, specifying that words and logos marked with ® or ™ are registered trademarks.

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Preface

Feedback

ARM welcomes feedback on the PrimeCell UART (PL011) and its documentation.

Feedback on this product

If you have any comments or suggestions about this product, contact your supplier and

give:

• the product name

• a concise explanation.

Feedback on this manual

If you have any comments on this manual, send an email to

errata@arm.com

. Give:

• the title

• the number

• the relevant page number(s) to which your comments apply

• a concise explanation of your comments.

ARM also welcomes general suggestions for additions and improvements.

Chapter 1

Introduction

This chapter introduces the UART (PL011). It contains the following sections:

• About the UART on page 1-2.

• Product revisions on page 1-5.

Introduction

1.1 About the UART

The UART is an Advanced Microcontroller Bus Architecture (AMBA) compliant

System-on-Chip (SoC) peripheral that is developed, tested, and licensed by ARM.

The UART is an AMBA slave module that connects to the Advanced Peripheral Bus

(APB). The UART includes an Infrared Data Association (IrDA) Serial InfraRed (SIR)

protocol ENcoder/DECoder (ENDEC).

The features of the UART are described in the following sections:

• Features

• Programmable parameters on page 1-3

• Variations from the 16C650 UART on page 1-4.

Note

Because of changes in the programmers model, the UART (PL011) is not backwards

compatible with the previous PrimeCell UART (PL010).

1.1.1 Features

The UART provides:

• Compliance to the AMBA Specification (Rev 2.0) onwards for easy integration

into SoC implementation.

• Programmable use of UART or IrDA SIR input/output.

• Separate 32×8 transmit and 32×12 receive First-In, First-Out (FIFO) memory

buffers to reduce CPU interrupts.

• Programmable FIFO disabling for 1-byte depth.

• Programmable baud rate generator. This enables division of the reference clock

by (1×16) to (65535×16) and generates an internal ×16 clock. The divisor can be

a fractional number enabling you to use any clock with a frequency >3.6864MHz

as the reference clock.

• Standard asynchronous communication bits (start, stop and parity). These are

added prior to transmission and removed on reception.

• Independent masking of transmit FIFO, receive FIFO, receive timeout, modem

status, and error condition interrupts.

• Support for Direct Memory Access (DMA).

• False start bit detection.

Introduction

• Line break generation and detection.

• Support of the modem control functions CTS, DCD, DSR, RTS, DTR, and RI.

• Programmable hardware flow control.

• Fully-programmable serial interface characteristics:

— data can be 5, 6, 7, or 8 bits

— even, odd, stick, or no-parity bit generation and detection

— 1 or 2 stop bit generation

— baud rate generation, dc up to UARTCLK/16

• IrDA SIR ENDEC block providing:

— programmable use of IrDA SIR or UART input/output

— support of IrDA SIR ENDEC functions for data rates up to 115200 bps

half-duplex

— support of normal

and low-power (1.41-2.23µs) bit durations

— programmable division of the UARTCLK reference clock to generate the

appropriate bit duration for low-power IrDA mode.

• Identification registers that uniquely identify the UART. These can be used by an

operating system to automatically configure itself.

1.1.2 Programmable parameters

The following key parameters are programmable:

• communication baud rate, integer, and fractional parts

• number of data bits

• number of stop bits

• parity mode

• FIFO enable (32 deep) or disable (1 deep)

• FIFO trigger levels selectable between

, and

• internal nominal 1.8432MHz clock frequency (1.42-2.12MHz) to generate

low-power IrDA mode shorter bit duration

• hardware flow control.

Additional test registers and modes are implemented for integration testing.

Introduction

1.1.3 Variations from the 16C650 UART

The UART varies from the industry-standard 16C650 UART device as follows:

• receive FIFO trigger levels are

, and

• transmit FIFO trigger levels are

, and

• the internal register map address space, and the bit function of each register differ

• the deltas of the modem status signals are not available.

The following 16C650 UART features are not supported:

• 1.5 stop bits (1 or 2 stop bits only are supported)

• independent receive clock.

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