ADuM1201：集成高性能双通道数字隔离器
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更新于2024-07-15
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ADuM1201是一款专为数字通信应用设计的高性能双通道数字隔离器，由Analog Devices（ADI）公司采用先进的iCoupler®技术开发。这款隔离器将高速CMOS技术和单芯片变压器技术集成在小巧的窄体SOIC8引脚封装中，旨在提供出色的隔离性能，同时保持低功耗和高数据速率传输能力。
ADuM1201的核心特性包括：
1. 集成度高：通过集成两个独立的通道，每个通道支持双向通信，这使得它在需要隔离不同电压等级信号的应用中非常实用，如5V与3V系统之间的接口。
2. 低功耗设计：在不同工作条件下，每个通道的电流消耗有所不同。在较低的数据速率（0Mbps到2Mbps）下，每通道最大电流为1.1mA或0.8mA，随着速率提升至10Mbps和25Mbps，电流分别增加到3.7mA、2.2mA和4.8mA。这种设计有助于延长设备的电池寿命，对于便携式或能源受限的设备尤为关键。
3. 电压转换：ADuM1201具备3V/5V的电压级别转换功能，能够有效地兼容不同的电源环境，并确保信号在隔离过程中的准确传递。
4. 高温耐受性：这款隔离器能够在高达105°C的温度下稳定运行，确保在各种恶劣环境下仍能维持良好的性能。
5. 高速数据传输：支持高达25Mbps的非归零（NRZ）数据速率，适合对传输速度有较高要求的实时通信应用，如工业自动化、电信系统或数据中心互联。
6. 可靠性与合规性：ADI公司提供的信息虽然被认为是准确和可靠的，但用户需注意可能存在专利权或第三方权利的问题，因此在实际应用中应确保遵循所有相关法律法规。
ADuM1201凭借其优越的隔离性能、低功耗特性和宽广的工作温度范围，成为数字通信系统设计中值得信赖的选择。其紧凑的封装形式和高效的通信能力，使得它在现代电子设备中扮演了至关重要的角色，尤其在需要信号隔离且追求高效能的领域。
ADuM1200/ADuM1201
Rev. B | Page 4 of 20
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM120xBR
Minimum Pulse Width
2
PW 100 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
10 Mbps C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
20 50 ns C
L
= 15 pF, CMOS signal levels
Pulse-Width Distortion, |t
PLH
− t
PHL
|
4
PWD 3 ns C
L
= 15 pF, CMOS signal levels
Change Versus Temperature 5 ps/°C C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
15 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels
6
t
PSKCD
3 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing Directional Channels
6
t
PSKOD
15 ns C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) t
R
/t
F
2.5 ns C
L
= 15 pF, CMOS signal levels
ADuM120xCR
Minimum Pulse Width
2
PW 20 40 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
25 50 Mbps C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
20 45 ns C
L
= 15 pF, CMOS signal levels
Pulse-Width Distortion, |t
PLH
– t
PHL
|
4
PWD 3 ns C
L
= 15 pF, CMOS signal levels
Change Versus Temperature 5 ps/°C C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
15 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels
6
t
PSKCD
3 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing Directional Channels
6
t
PSKOD
15 ns C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) t
R
/t
F
2.5 ns C
L
= 15 pF, CMOS signal levels
For All Models
Common-Mode Transient Immunity
at Logic High Output
7
|CM
H
| 25 35 kV/µs
V
Ix
= V
DD1
, V
DD2
, V
CM
= 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity
at Logic Low Output
7
|CM
L
| 25 35 kV/µs
V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
Refresh Rate f
r
1.2 Mbps
Input Dynamic Supply Current, per Channel
8
I
DDI (D)
0.19 mA/Mbps
Output Dynamic Supply Current, per Channel
8
I
DDO (D)
0.05 mA/Mbps
1
The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See
Figure 6 through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through Figure 11
for total I
Figure 8
Figure 8
Figure 9
DD1
and I
DD2
supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.
2
The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
4
t
PHL
propagation delay is measured from the 50% level of the falling edge of the V
Ix
signal to the 50% level of the falling edge of the V
Ox
signal. t
PLH
propagation delay is
measured from the 50% level of the rising edge of the V
Ix
signal to the 50% level of the rising edge of the V
Ox
signal.
5
t
PSK
is the magnitude of the worst-case difference in t
PHL
and/or t
PLH
that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
CM
H
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD2
. CM
L
is the maximum common-mode voltage slew rate
that can be sustained while maintaining V
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for
information on per-channel supply current for unloaded and loaded conditions. See the section for guidance on calculating per-channel supply
current for a given data rate.
Figure 6
Power Consumption
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