EZ-USB FX3 SuperSpeed USB Controller - C57294_CYUSB3014-BZXI规格详解

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"C57294_CYUSB3014-BZXI是 Cypress Semiconductor 公司生产的USB 3.0传输芯片，该芯片详细规格书中涵盖了其在高速数据传输、通用串行总线集成以及通用可编程接口等多个方面的特性。这款芯片的主要特点包括： 1. **USB 3.1 Gen 1 和 USB 2.0 集成**：它符合USB 3.1 Specification Revision 1.0标准，支持5-Gbps的SuperSpeed PHY，同时兼容HS-OTG（高速On-The-Go）主机和外围设备，与OTG Supplement Version 2.0规范一致。 2. **32个物理端点**：提供了32个物理端点，使得设备能够处理更多并发的数据传输任务。 3. **电池充电支持**：芯片支持电池充电规格1.1，同时具备配件充电适配器（ACA）检测功能，方便移动设备的充电需求。 4. **通用可编程接口 (GPIF™ II)**：GPIF II是一个可编程的100-MHz接口，能与各种外部设备连接，数据总线宽度支持8、16、24和32位，并且可以配置多达16个控制信号，增强了硬件接口的灵活性。 5. **内置32位CPU**：采用ARM926EJ核心，运行频率高达200 MHz，内建512-KB或256-KB的嵌入式SRAM，提供强大的数据处理能力。 6. **额外的外设连接**：支持SPI主设备模式，最高可达33MHz的时钟速度；UART接口支持高达4Mbps的数据速率；I2C主控制器工作在1MHz，以及I2S主发射器，采样频率可根据需求调整。 C57294_CYUSB3014-BZXI是一款高度集成的USB 3.0控制器，适用于需要高速数据传输和多样化接口应用的场合，如消费电子、工业控制、移动设备等领域。其丰富的接口选项和强大的处理能力使其在设计中具有极高的灵活性和适应性。"

CYUSB301X/CYUSB201X

Document Number: 001-52136 Rev. *R Page 9 of 52

UART Interface

The UART interface of FX3 supports full-duplex communication.

It includes the signals noted in Ta ble 1 .

The UART is capable of generating a range of baud rates, from

300 bps to 4608 Kbps, selectable by the firmware. If flow control

is enabled, then FX3's UART only transmits data when the CTS

input is asserted. In addition to this, FX3’s UART asserts the RTS

output signal, when it is ready to receive data.

C Interface

FX3’s I

C interface is compatible with the I

C Bus Specification

Revision 3. This I

C interface is capable of operating only as I

master; therefore, it may be used to communicate with other I

slave devices. For example, FX3 may boot from an EEPROM

connected to the I

C interface, as a selectable boot option.

FX3’s I

C Master Controller also supports multi-master mode

functionality.

The power supply for the I

C interface is VIO5, which is a

separate power domain from the other serial peripherals. This

gives the I

C interface the flexibility to operate at a different

voltage than the other serial interfaces.

The I

C controller supports bus frequencies of 100 kHz,

400 kHz, and 1 MHz. When VIO5 is 1.2 V, the maximum

operating frequency supported is 100 kHz. When VIO5 is 1.8 V,

2.5 V, or 3.3 V, the operating frequencies supported are 400 kHz

and 1 MHz. The I

C controller supports clock-stretching to

enable slower devices to exercise flow control.

The I

C interface’s SCL and SDA signals require external pull-up

resistors. The pull-up resistors must be connected to VIO5.

S Interface

FX3 has an I

S port to support external audio codec devices.

FX3 functions as I

S Master as transmitter only. The I

S interface

consists of four signals: clock line (I2S_CLK), serial data line

(I2S_SD), word select line (I2S_WS), and master system clock

(I2S_MCLK). FX3 can generate the system clock as an output

on I2S_MCLK or accept an external system clock input on

I2S_MCLK.

The sampling frequencies supported by the I

S interface are

32 kHz, 44.1 kHz, and 48 kHz.

Boot Options

FX3 can load boot images from various sources, selected by the

configuration of the PMODE pins. Following are the FX3 boot

options:

■ Boot from USB

■ Boot from I

■ Boot from SPI (SPI devices supported are M25P32 (32 Mbit),

M25P16 (16 Mbit), M25P80 (8 Mbit), and M25P40 (4 Mbit)) or

their equivalents

■ Boot from GPIF II ASync ADMux mode

■ Boot from GPIF II Sync ADMux mode

■ Boot from GPIF II ASync SRAM mode

Reset

Hard Reset

A hard reset is initiated by asserting the Reset# pin on FX3. The

specific reset sequence and timing requirements are detailed in

Figure 30 on page 42 and Table 19 on page 42. All I/Os are

tristated during a hard reset. Note however, that the on-chip

bootloader has control after a hard reset and it will configure I/O

signals depending on the selected boot mode; see AN76405 -

EZ-USB® FX3™ Boot Options for more details.

Soft Reset

In a soft reset, the processor sets the appropriate bits in the

PP_INIT control register. There are two types of Soft Reset:

■ CPU Reset – The CPU Program Counter is reset. Firmware

does not need to be reloaded following a CPU Reset.

■ Whole Device Reset – This reset is identical to Hard Reset.

■ The firmware must be reloaded following a Whole Device

Reset.

Table 1. UART Interface Signals

Signal Description

TX Output signal

RX Input signal

CTS Flow control

RTS Flow control

Table 2. FX3 Booting Options

PMODE[2:0]

[1]

Boot From

F00 Sync ADMux (16-bit)

F01 Async ADMux (16-bit)

F11 USB boot

F0F Async SRAM (16-bit)

F1F I

C, On Failure, USB Boot is Enabled

1FF I

C only

0F1 SPI, On Failure, USB Boot is Enabled

Note

1. F indicates Floating.

CYUSB301X/CYUSB201X

Document Number: 001-52136 Rev. *R Page 10 of 52

Clocking

FX3 allows either a crystal to be connected between the XTALIN

and XTALOUT pins or an external clock to be connected at the

CLKIN pin. The XTALIN, XTALOUT, CLKIN, and CLKIN_32 pins

can be left unconnected if they are not used.

Crystal frequency supported is 19.2 MHz, while the external

clock frequencies supported are 19.2, 26, 38.4, and 52 MHz.

FX3 has an on-chip oscillator circuit that uses an external

19.2-MHz (±100 ppm) crystal (when the crystal option is used).

An appropriate load capacitance is required with a crystal. Refer

to the specification of the crystal used to determine the appro-

priate load capacitance. The FSLC[2:0] pins must be configured

appropriately to select the crystal- or clock-frequency option. The

configuration options are shown in Table 3.

Clock inputs to FX3 must meet the phase noise and jitter require-

ments specified in Table 4 on page 10.

The input clock frequency is independent of the clock and data

rate of the FX3 core or any of the device interfaces. The internal

PLL applies the appropriate clock multiply option depending on

the input frequency.

32-kHz Watchdog Timer Clock Input

FX3 includes a watchdog timer. The watchdog timer can be used

to interrupt the ARM926EJ-S core, automatically wake up the

FX3 in Standby mode, and reset the ARM926EJ-S core. The

watchdog timer runs a 32-kHz clock, which may be optionally

supplied from an external source on a dedicated FX3 pin.

The firmware can disable the watchdog timer. Requirements for

the optional 32-kHz clock input are listed in Ta b le 5.

Power

FX3 has the following power supply domains:

■ IO_VDDQ: This is a group of independent supply domains for

digital I/Os. The voltage level on these supplies is 1.8 V to 3.3 V.

FX3 provides six independent supply domains for digital I/Os

listed as follows (see Ta b le 7 on page 15 for details on each of

the power domain signals):

❐ VIO1: GPIF II I/O

❐ VIO2: IO2

❐ VIO3: IO3

❐ VIO4: UART-/SPI/I

❐ VIO5: I

C and JTAG (supports 1.2 V to 3.3 V)

❐ CVDDQ: This is the supply voltage for clock and reset I/O. It

should be either 1.8 V or 3.3 V based on the voltage level of

the CLKIN signal.

❐ V

: This is the supply voltage for the logic core. The nominal

supply-voltage level is 1.2 V. This supplies the core logic

circuits. The same supply must also be used for the following:

• AVDD: This is the 1.2-V supply for the PLL, crystal oscilla-

tor, and other core analog circuits

• U3TXVDDQ/U3RXVDDQ: These are the 1.2-V supply volt-

ages for the USB 3.0 interface.

■ VBATT/VBUS: This is the 3.2-V to 6-V battery power supply

for the USB I/O and analog circuits. This supply powers the

USB transceiver through FX3's internal voltage regulator.

VBATT is internally regulated to 3.3 V.

Table 3. Crystal/Clock Frequency Selection

FSLC[2] FSLC[1] FSLC[0]

Crystal/Clock

Frequency

0 0 0 19.2-MHz crystal

1 0 0 19.2-MHz input CLK

1 0 1 26-MHz input CLK

1 1 0 38.4-MHz input CLK

1 1 1 52-MHz input CLK

Table 4. FX3 Input Clock Specifications

Parameter Description

Specification

Units

Min Max

Phase noise

100-Hz offset – –75

1-kHz offset – –104

10-kHz offset – –120

100-kHz offset – –128

1-MHz offset – –130

Maximum frequency deviation – – 150 ppm

Duty cycle – 30 70

%Overshoot – – 3

Undershoot – – –3

Rise time/fall time – – 3 ns

Table 5. 32-kHz Clock Input Requirements

Parameter Min Max Units

Duty cycle 40 60 %

Frequency deviation – ±200 ppm

Rise time/fall time – 200 ns

CYUSB301X/CYUSB201X

Document Number: 001-52136 Rev. *R Page 11 of 52

Power Modes

FX3 supports the following power modes:

■ Normal mode: This is the full-functional operating mode. The

internal CPU clock and the internal PLLs are enabled in this

mode.

❐ Normal operating power consumption does not exceed the

sum of I

Core max and I

USB max (see Tab l e 7 on page

15 for current consumption specifications).

❐ The I/O power supplies VIO2, VIO3, VIO4, and VIO5 can be

turned off when the corresponding interface is not in use.

VIO1 cannot be turned off at any time if the GPIF II interface

is used in the application.

■ Low-power modes (see Ta b le 6 on page 11):

❐ Suspend mode with USB 3.0 PHY enabled (L1)

❐ Suspend mode with USB 3.0 PHY disabled (L2)

❐ Standby mode (L3)

❐ Core power-down mode (L4)

Table 6. Entry and Exit Methods for Low-Power Modes

Low-Power Mode Characteristics Methods of Entry Methods of Exit

Suspend Mode with

USB 3.0 PHY

Enabled (L1)

■ The power consumption in this mode does

not exceed ISB

■ USB 3.0 PHY is enabled and is in U3 mode

(one of the suspend modes defined by the

USB 3.0 specification). This one block

alone is operational with its internal clock

while all other clocks are shut down

■ All I/Os maintain their previous state

■ Power supply for the wakeup source and

core power must be retained. All other

power domains can be turned on/off

individually

■ The states of the configuration registers,

buffer memory, and all internal RAM are

maintained

■ All transactions must be completed before

FX3 enters Suspend mode (state of

outstanding transactions are not

preserved)

■ The firmware resumes operation from

where it was suspended (except when

woken up by RESET# assertion) because

the program counter does not reset

■ Firmware executing on

ARM926EJ-S core can put FX3 into

suspend mode. For example, on

USB suspend condition, firmware

may decide to put FX3 into suspend

mode

■ External Processor, through the use

of mailbox registers, can put FX3 into

suspend mode

■ D+ transitioning to low

or high

■ D- transitioning to low

or high

■ Impedance change on

OTG_ID pin

■ Resume condition on

SSRX±

■ Detection of VBUS

■ Level detect on

UART_CTS

(programmable

polarity)

■ GPIF II interface

assertion of CTL[0]

■ Assertion of RESET#

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