Actel ProASIC3 Flash FPGA: High Capacity, Reprogrammable Technology

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"Actel A3P 数据表" Actel A3P系列是Actel公司推出的基于闪存技术的现场可编程门阵列（FPGA）产品，具有高容量、可重新编程、低功耗和高性能等特性。该数据表详细介绍了A3P FPGA家族的主要功能和优势。 1. 高容量：A3P FPGA提供了从30千系统门到1百万系统门的广泛容量选择，满足不同复杂度设计的需求。此外，它还配备了高达144千位的真正双端口静态随机存取存储器（SRAM），这使得A3P非常适合需要大量内部存储的应用，如缓存或数据处理。 2. 大量用户输入/输出（I/O）：每个A3P FPGA提供多达288个用户I/O引脚，这允许设计者实现更复杂的接口方案，同时还能保持布局的灵活性。 3. 可重新编程的闪存技术：采用130纳米7层金属（6铜）的闪存基CMOS工艺，A3P FPGA支持在电源开启时即用（Live-At-Power-Up）的Level 0功能，这意味着设计可以在上电后立即运行。更重要的是，即使在断电状态下，它也能保留编程的设计，确保了设计的持久性和可靠性。 4. 在系统编程（ISP）和安全性：A3P FPGA支持通过JTAG接口进行安全的在系统编程，采用128位AES解密，符合IEEE 1532标准（A3P030除外）。此外，FlashLock功能可以保护FPGA内的设计内容不被未经授权的访问。 5. 低功耗：A3P FPGA支持1.5V核心电压，适用于低功耗系统。它还可以与1.5V-only系统兼容，而且采用低阻抗闪存开关，进一步降低了功耗。 6. 高性能路由结构：A3P FPGA采用分段化的层次化路由和时钟结构，结合超快的局部和长线网络，以及增强的高速、超长线网络，确保了内部信号的快速传输和高效的时钟管理。 7. 其他特性：除了上述特点，Actel A3P FPGA还提供了其他功能，如非易失性用户内存（FROM）、可编程逻辑块、宏单元、分布式RAM和乘法器等，以支持各种高级应用。 Actel A3P系列是面向需要高性能、大容量、低功耗以及高度安全性的嵌入式系统设计的理想选择。这款FPGA产品结合了先进的工艺技术和丰富的内置功能，能够满足广泛的电子设计需求。

ProASIC3 Flash Family FPGAs

2-6 Advanced v0.2

Routing Architecture

Routing Resources

The routing structure of ProASIC3 devices is designed to

provide high performance through a flexible four-level

hierarchy of routing resources: ultra-fast local resources,

efficient long-line resources, high-speed, very-long-line

resources, and the high-performance VersaNet networks.

The ultra-fast local resources are dedicated lines that allow

the output of each VersaTile to connect directly to every

input of the eight surrounding VersaTiles (Figure 2-6). The

exception to this is that the SET/CLR input of a VersaTile

configured as a D-type flip-flop is driven only by the

VersaTile global network.

The efficient, long-line resources provide routing for

longer distances and higher fanout connections. These

resources vary in length (spanning 1, 2, or 4 VersaTiles),

run both vertically and horizontally, and cover the entire

ProASIC3 device (Figure 2-7 on page 2-7). Each VersaTile

can drive signals onto the efficient long-line resources,

which can access every input of every VersaTile. Active

buffers are inserted automatically by routing software to

limit the loading effects.

The high-speed, very-long-line resources, which span the

entire device with minimal delay, are used to route very

long or high-fanout nets: length +/–12 VersaTiles in the

vertical direction and length +/–16 in the horizontal

direction from a given core VersaTile (Figure 2-8 on page

2-8). Very long lines in ProASIC3 devices have been

enhanced over those in previous ProASIC families. This

provides a significant performance boost for long-reach

signals.

The high-performance VersaNet global networks are

low-skew, high-fanout nets that are accessible from

external pins or from internal logic (Figure 2-9 on page

2-9). These nets are typically used to distribute clocks,

resets, and other high-fanout nets requiring minimum

skew. The VersaNet networks are implemented as clock

trees, and signals can be introduced at any junction.

These can be employed hierarchically with signals

accessing every input on all VersaTiles.

Note: Input to the core cell for the D-flip-flop set and reset is only available via the VersaNet global network connection.

Figure 2-6 • Ultra-Fast Local Lines Connected to the Eight Nearest Neighbors

Inputs

Output

Ultra-Fast Local Lines

(connects a VersaTile to the

adjacent VersaTile, I/O buffer,

or memory block)

Long Lines

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ProASIC3 Flash Family FPGAs

Advanced v0.2 2-9

Clock Resources (VersaNets)

ProASIC3 devices offer powerful and flexible control of

circuit timing through the use of analog circuitry. Each

chip has up to six CCCs. The west CCC also contains a

phase-locked loop (PLL) core, delay lines, phase shifter

(0°, 90°, 180°, 270°), and clock multiplier/dividers. Each

CCC has all the circuitry needed for the selection and

interconnection of inputs to the VersaNet global

network. The east and west CCCs each have access to

three VersaNet global lines on each side of the chip (six

total lines).

Advantages of the VersaNet Approach

One of the architectural benefits of ProASIC3 is the set of

powerful and low-delay VersaNet global networks.

ProASIC3 offers six chip (main) global networks that are

distributed from the center of the FPGA array (Figure 2-9).

In addition, ProASIC3 devices have three regional globals

in each of the four chip quadrants. Each core VersaTile has

access to nine global network resources: three quadrant

and six chip (main) global networks, and a total of 18

globals on the device. Each of these networks contain

spines and rows that reach all the VersaTiles in the

quadrants (Figure 2-10 on page 2-10). This flexible

VersaNet global network architecture allows users to map

up to 144 different internal/external clocks in a ProASIC3

device. Details on the VersaNet networks are given in

Table 2-2 on page 2-10. The flexible use of the ProASIC3

VersaNet global network allows the designer to address

several design requirements. User applications that are

clock-resource-intensive can easily route external or gated

internal clocks using VersaNet global routing networks.

Designers can also drastically reduce delay penalties and

minimize resource usage by mapping critical, high-fanout

nets to the VersaNet global network.

In A3P030 devices, all six VersaNets come from the North

edge of the FPGA fabric. The A3P030 does not support

the VersaNet global network concept of top and bottom

spines due to the limited gate density of this part.

Note: Not applicable to the A3P030 device.

Figure 2-9 • Overview of ProASIC3 VersaNet Global Network

Quadrant Global Pads

Top Spine

Bottom Spine

Pad Ring

I/O RING

I/O Ring

Chip (main)

Global Pads

Spine-Selection

Tree MUX

Global

Pads

High-Performance

VersaNet Global Network

Main (chip)

Global Networ

Global Spine

Global Ribs

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ProASIC3 Flash Family FPGAs

2-10 Advanced v0.2

VersaNet Global Networks and Spine Access

The ProASIC3 architecture contains nine segmented

global networks that can access all the VersaTiles, SRAM

memory, and I/O tiles on the ProASIC3 device. These

VersaNet global networks offer fast, low-skew routing

resources for high-fanout nets, including clock signals. In

addition, these highly-segmented global networks offer

users the flexibility to create low-skew local networks

using spines for up to 144 internal/external clocks (in an

A3P1000 device) or other high-fanout nets in ProASIC3

devices. Optimal usage of these low-skew networks can

result in significant improvement in design performance

on ProASIC3 devices.

The nine spines available in a vertical column reside in

global networks with two separate regions of scope: the

quadrant global network, which has three spines, and

the chip (main) global network, which has six spines.

There are four quadrant global network regions per

device (Figure 2-10).

The spines are the vertical branches of the global

network tree, shown in Figure 2-11 on page 2-11. Each

spine in a vertical column of a chip (main) global

network is further divided into two spine segments: one

in the top and one in the bottom half of the die. Top and

Note: This does not apply to the A3P030, since the VersaNet global network is sourced only for the north edge of the FPGA fabric.

Figure 2-10 • Global Network Architecture

Table 2-2 • ProASIC3 Globals/Spines/Rows by Device

A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000

Global VersaNets (Trees)* 6 9 9 9 9 9 9

VersaNet Spines/Tree 4 4 4 8 8 12 16

Total Spines 24 36 36 72 72 108 144

VersaTiles in Each Top or Bottom Spine 384 384 384 768 768 1,152 1,536

Total VersaTiles 768 1,536 3,072 6,144 9,216 13,824 24,576

Note: *There are six chip (main) globals and three globals per quadrant (except in the A3P030 device).

North Quadrant Global Network

South Quadrant Global Network

Chip (main)

Global

Network

333

Global Spine Quadrant Global Spine

CCC

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