TI-BQ79606A-Q1：集成汽车电池保护器与SafeTI技术

需积分: 9 2 浏览量更新于2024-06-30 4 收藏 4.67MB PDF 举报

TI-BQ79606A-Q1是一款专为汽车应用设计的精密电源管理集成电路，它集成了硬件保护功能，满足了严格的AEC-Q100标准，适用于电池组系统，确保在极端环境温度下(-40°C 至 +105°C)的可靠运行。该器件具有高级的安全特性，如： 1. **温度与电压监控** - BQ79606A具有温度和电压监控功能，符合SafeTI™-26262 ASIL-D标准，确保系统的安全性。它能精确测量电池电压，误差范围低至±1.1mV，并支持失调电压补偿。 2. **通信功能** - 该IC具备先进的通信接口，包括UART和CAN (Controller Area Network)接口，使得数据传输更为高效和稳定。此外，它还支持同步电池电压测量，能在极短时间内（1ms）完成对大量电池（最多96节）的精确测量。 3. **故障检测** - 设备内置故障检测机制，如COMLFAULT和LCOMHFAULT，即使在通信线路中断的情况下，通过可选的环形连接结构仍能保持一定程度的堆叠通信。 4. **信号处理** - 它配备低至1.2Hz的可配置数字低通滤波器，有助于过滤噪声，提升信号质量。同时，该IC可以监控多个电池连接以及NTC/辅助通道，增强系统对电池状态的全面监测。 5. **集成ADC** - 内置16位模数转换器(ADC)，提高了数据采集的精度和效率，对于需要精确电压测量和数据分析的应用来说，这是不可或缺的一部分。 6. **硬件保护** - 该IC针对汽车应用中的电气过载和电磁兼容性进行了优化，确保设备在严苛的环境下能够正常工作，符合HBMESD分类等级2和CDMESD分类等级C4B。 BQ79606A-Q1是一款高度集成且安全可靠的电源管理解决方案，适用于对电池管理系统有严格要求的汽车电子系统设计，为用户提供了全面的电池电压管理、故障检测和通信能力。设计者在使用前，务必参考英文原版数据手册获取最新的规格和建议，因为TI公司强调其提供的中文版本可能存在不准确或不完整之处。

BQ79606A-Q1

ZHCSJM7 –APRIL 2019

www.ti.com.cn

Timing Requirements (continued)

BAT

= 5.5V to 30V, all LDOs operating in regulation, Typical Applications Circuit used, 3 to 6 cells connected, –40°C to

+105°C free-air temperature range (unless otherwise noted)

PARAMETERS TEST CONDITIONS MIN NOM MAX UNIT

WAKE

WAKE tone sending duration V

BAT

> 4.75V 40 pulses

SLPtoACTDET

SLEEPtoACTIVE tone receive threshold V

BAT

> 4.75V 20 pulses

SLPtoACT

SLEEPtoACTIVE tone sending duration V

BAT

> 4.75V 40 pulses

SHDNDET

SHUTDOWN tone receive threshold V

BAT

> 4.75V 100 pulses

SHDN

SHUTDOWN tone sending duration V

BAT

> 4.75V 185 pulses

FLTTONEDET

Fault tone detection threshold V

BAT

> 4.75V, fault condition present 20 pulses

FLTONE

Fault tone sending duration V

BAT

> 4.75V, fault condition present 40 pulses

FLTRETRY

Fault tone retry during persistent fault

condition

BAT

> 4.75V, fault condition present 50 ms

FLTHBDET

Heartbeat tone detection threshold

BAT

> 4.75V, no fault present, heartbeat

enabled

20 pulses

HBTONE

Heartbeat tone sending duration

BAT

> 4.75V, no fault present, heartbeat

enabled

40 pulses

WAITHB

Time between heartbeat tones

BAT

> 4.75V, no fault present, heartbeat

enabled

400 ms

HBTO

Heartbeat fault timeout

BAT

> 4.75V, fault signaled if no

heartbeat received with t

HBTO

1 s

HBFAST

Heartbeat received to fast threshold

BAT

> 4.75V, fault signaled if the time

between heartbeat tones is less than

HBFAST

200 ms

FLTTONE_HI

Fault pulse high time (analog delay

based)

1 µs

FLTTONE_LO

Fault pulse low time 1 µs

FLTTONE

Time between pulses within a fault tone

(LFO based). From the begning of a

pulse untill the begining of the next

pulse.

11.5 µs

COMTONE

Time between pulses within a comms

tone (HFO based). From the begning of a

pulse untill the begining of the next

pulse.

11 µs

TONE_HI

Comms pulse high time (HFO based) 1 µs

TONE_LO

Comms pulse low time (HFO based) 1 µs

FTS_Latency

Fault Tone Latency in stack device

Latency from fault tone received/detected

to fault tone going out in a stack device.

48 µs

FTB_Latency

Fault Tone Latency in base device

Latency from fault tone received/detected

in base device to NFAULT tone going

out.

24 µs

UART Interface

RXTX

BAUD

RX/TX signaling rate adjustable range V

BAT

> 4.75V 125 1000 kbps

ERR

BD(RX)

Input baud rate error V

BAT

> 4.75V –1.5% 1.5%

ERR

BD(TX)

Output baud rate error V

BAT

> 4.75V –1.5% 1.5%

UART(BRK)

Communications clear (break) time V

BAT

> 4.75V 15 20 bit periods

UART(StA)

SLEEPtoACTIVE time V

BAT

> 4.75V, RX held low 250 300 µs

UART(RST)

Communications reset time V

BAT

> 4.75V, RX held low 450 µs

UART(RXMIN)

Minimum RX high time after

Communications Clear received

1 bit periods

Safety Diagnostics

VIOUVDGL

Under-voltage deglitch on VIO

VIO

rising. V

VIO

< V

VIOUV

threshold to

corresponding flag set

25 µs

OVDGL

Over-voltage deglitch on supply rails

(AVDD, DVDD)

SUPPLY

rising. V

SUPPLY

> VOV threshold

to corresponding flag set

25 µs

OVCVDDDGL

Over-voltage deglitch on VLDO supply

rail

VLDO

rising. V

VLDO

> VOV threshold to

corresponding flag set

250 µs

UVDGL

Under-voltage deglitch on supply rails

(AVDD, CVDD)

SUPPLY

falling. V

SUPPLY

< VUV threshold

to corresponding flag set

25 µs

BQ79606A-Q1

ZHCSJM7 –APRIL 2019

www.ti.com.cn

8.3 Feature Description

This section includes the descriptions of the individual blocks found in the BQ79606A-Q1 device.

8.3.1 Power Supplies

The BQ79606A-Q1 generates all of the required supplies for operation. There are 3 integrated LDO supplies as

well as a buffered reference to supply the bias for the GPIO* NTC monitoring linearization ciruits (for temperature

sensing).

8.3.1.1 AVDD LDO

The AVDD low dropout regulator (LDO) is the supply for the analog circuits in the BQ79606A-Q1. The supply for

AVDD comes from LDOIN. AVDD contains an over-voltage comparator that signals a fault

(RAIL_FAULT[AVDDOV]) when the voltage at AVDD rises above V

AVDDOV

. Additionally, AVDD contains an

under-voltage circuit that sends the IC into Digital Reset when AVDD drops below V

AVDDUV

. Upon restarting, a

fault is indicated (RAIL_FAULT[AVDDUV_DRST]) to inform the host why the IC failed. Additionally, AVDD is

continuously monitored for abnormal oscillations that can result in undesired operation. If such an oscillation

occurs, the SYS_FAULT2[AVDD_OSC] bit is set.

8.3.1.2 VLDO LDO

The VLDO low dropout regulator (LDO) is the supply for the daisy chain transceiver circuits in the BQ79606A-Q1.

The supply for VLDO comes from LDOIN. VLDO contains an overvoltage comparator that signals a fault

(RAIL_FAULT[VLDOOV]) when the voltage at VLDO rises above V

VLDOOV

8.3.1.3 DVDD LDO

The DVDD low dropout regulator (LDO) is the supply for the digital circuits in the BQ79606A-Q1. The supply for

DVDD comes from LDOIN. DVDD contains an overvoltage comparator that signals a fault

(RAIL_FAULT[DVDDOV]) when the voltage at DVDD rises above V

DVDDOV

. Additionally, DVDD contains a

comparator that sets digital in reset mode if DVDD drops below V

DRDVDD

. Additionally, the DVSS pin is monitored

continuously and the SYS_FAULT2[DVSS_OPEN] bit is set if an 'open' condition is detected for DVSS.

8.3.1.4 TSREF

The TSREF is a 2.5V buffered REF1 reference that supplies the GPIO* linearization circuits when measuring

external temperature sensors. This allows the ADC to operate from the same reference and provide a ratiometric

result for GPIO*. TSREF is capable of supplying up to I

TSREF

current limit and must not be used to power any

circuits other than the resistor dividers for GPIO*. Enable TSREF using the CONTROL2[TSREF_EN] bit. The

startup time for TSREF is determined by the external capacitance and the current limit. The time is calculated

using the simple capacitor charging equation. No GPIO measurements should be taken until TSREF is settled at

the regulation point.

See Ratiometric Measurement Configuration for details on selecting the resistors. TSREF contains an over-

voltage comparator that signals a fault (RAIL_FAULT[TSREFOV]) when the voltage at TSREF rises above

TSREFOV

. Additionally, TSREF contains an under-voltage circuit that signals a fault (RAIL_FAULT[TSREFUV])

when TSREF drops below V

TSREFUV

. Additionally, TSREF is continuously monitored for abnormal oscillations that

can result in undersired operation. If such an oscillation occurs, the SYS_FAULT2[TSREF_OSC] bit is set.

8.3.1.5 Internal Supply Rails

AVAO_REF (Analog Voltage Always On) is a fully internal rail that runs from the BAT input. It powers low current

circuits that are required in all modes. AVAO_REF is continuously monitored for over and under voltage

conditions. The overvoltage comparator signals a fault (SYS_FAULT1[AVAO_REF_OV]) when the voltage at

AVAO_REF rises above V

AVAO_REF_OV

. Additionally, AVAO_REF contains an under-voltage circuit that puts the IC

into POR mode if V

AVAO_REF

drops below V

AVAO_REF_UV

8.3.1.6 CVDD and VIO Supplies

CVDD is the supply input for the daisy chain transceiver circuits. CVDD receives it's power externally from

VLDO. This allows for external filtering for noisy applications. CVDD is monitored for under-voltage constantly. If

CVDD

< V

CVDDUV

the RAIL_FAULT[CVDDUV] bit is set. Additionally, the CVSS pin is monitored continuously, and

the SYS_FAULT2[CVSS_OPEN] bit is set if an 'open' condition is detected for CVSS.

剩余267页未读，继续阅读

不觉明了

粉丝: 4555
资源: 5759

TI-BQ79606A-Q1：集成汽车电池保护器与SafeTI技术

TI-BQ79606-Q1.pdf

TI-BQ79656-Q1.pdf

TI-BQ79600-Q1.pdf

TI-BQ24105-Q1.pdf

TI-BQ29209-Q1.pdf

TI-BQ24392-Q1.pdf

TI-BQ79614-Q1.pdf

TI-BQ79631-Q1.pdf

TI-BQ79654-Q1：汽车级电池监控器与保护器，功能安全标准符合

TI bq79606-Q1 汽车电池组监控与硬件保护器

最新资源