PYTHON 5.0/2.0 MegaPixels 全球快门 CMOS 图像传感器

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PYTHON 5.0/2.0 MegaPixels 全球快门 CMOS 图像传感器 PYTHON 5.0/2.0 MegaPixels 全球快门 CMOS 图像传感器是一款高性能的图像传感器，具有全球快门功能，可以实现高帧率拍摄。该传感器具有多种数据输出选项，包括 8LVDS 数据通道和 4LVDS 数据通道等。同时，该传感器还具有低噪声全球快门像素、零行开销时间模式、高速串行接口等特点。数据输出选项： PYTHON 5.0/2.0 MegaPixels 全球快门 CMOS 图像传感器具有多种数据输出选项，包括： * P1−SN/SE/FN：8LVDS 数据通道 * P3−SN/SE：4LVDS 数据通道尺寸选项： PYTHON 5.0/2.0 MegaPixels 全球快门 CMOS 图像传感器具有多种尺寸选项，包括： * PYTHON2000：1920x1200 活动像素，2/3” 光学格式 * PYTHON5000：2592x2048 活动像素，1” 光学格式全球快门像素： PYTHON 5.0/2.0 MegaPixels 全球快门 CMOS 图像传感器具有 4.8μmx4.8μm 低噪声全球快门像素，可以实现高帧率拍摄。其他特点： PYTHON 5.0/2.0 MegaPixels 全球快门 CMOS 图像传感器还具有多种其他特点，包括： * 单色（SN）、彩色（SE）和近红外（FN）模式 * 零行开销时间模式，能够实现更高的帧率 * 帧率可达 100/85 帧每秒（Zero ROT/Non-Zero ROT）@ 5MP * 帧率可达 230/180 帧每秒（Zero ROT/Non-Zero ROT）@ 2MP * 帧率可达 255/200 帧每秒（Zero ROT/Non-Zero ROT）@ Full HD * 内置 10 位模拟数字转换器（ADC） * 八/四/二/一 LVDS 高速串行输出 * 随机可编程感兴趣区域（ROI）读取 * 串行外围接口（SPI） * 自动曝光控制（AEC） * 相位锁定环路（PLL） * 高动态范围（HDR）模式可能 PYTHON 5.0/2.0 MegaPixels 全球快门 CMOS 图像传感器是一款高性能的图像传感器，具有多种数据输出选项、尺寸选项和其他特点，能够满足各种图像采集应用的需求。

NOIP1SN5000A

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SENSOR OPERATION

Flowchart

Figure 15 shows the sensor operation flowchart. The sensor has six different ‘states’. Every state is indicated with the oval

circle. These states are Power off, Low power standby, Standby (1), Standby (2), Idle, Running.

Figure 15. Sensor Operation Flowchart

Power Up Sequence

Enable Clock Management - Part 2

(First Pass after Hard Reset)

Low-Power Standby

Required Register

Upload

Standby (2)

Soft Power-Up

Idle

Enable Sequencer

Running

Sensor (re-)configuration

(optional)

Disable Sequencer

Soft Power-Down

Disable Clock Management

Part 2

Power Off

Power Down

Sequence

Intermediate Standby

Enable Clock Management - Part 2

(Not First Pass after Hard Reset)

Sensor (re-)configuration

(optional)

Sensor (re-)configuration

(optional)

Assertion of reset_n Pin

Enable Clock Management - Part 1

Poll Lock Indication

(only when PLL is enabled)

Disable Clock Management

Part 1

Standby (1)

NOIP1SN5000A

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Sensor States

Low Power Standby

In low power standby state, all power supplies are on, but

internally every block is disabled. No internal clock is

running (PLL / LVDS clock receiver is disabled).

All register settings are set to their default values (see

Table 37).

Only a subset of the SPI registers is active for read/write

in order to be able to configure clock settings and leave the

low power standby state. The only SPI registers that should

be touched are the ones required for the ‘Enable Clock

Management’ action described in Enable Clock

Management − Part 1 on page 16

Standby (1)

In standby state, the PLL/LVDS clock receiver is running,

but the derived logic clock signal is not enabled.

Standby (2)

In standby state, the derived logic clock signal is running.

All SPI registers are active, meaning that all SPI registers

can be accessed for read or write operations. All other blocks

are disabled.

Idle

In the idle state, all internal blocks are enabled, except the

sequencer block. The sensor is ready to start grabbing

images as soon as the sequencer block is enabled.

Running

In running state, the sensor is enabled and grabbing

images. The sensor can be operated in global master/slave

modes.

User Actions: Power Up Functional Mode Sequences

Power Up Sequence

Figure 16 shows the power up sequence of the sensor. The

figure indicates that the first supply to ramp−up is the

vdd_18 supply, followed by vdd_33 and vdd_pix

respectively. It is important to comply with the described

sequence. Any other supply ramping sequence may lead to

high current peaks and, as consequence, a failure of the

sensor power up.

The clock input should start running when all supplies are

stabilized. When the clock frequency is stable, the reset_n

signal can be de−asserted. After a wait period of 10 ms, the

power up sequence is finished and the first SPI upload can

be initiated.

NOTE: The ‘clock input’ can be the CMOS PLL clock

input (clk_pll), or the LVDS clock input

(lvds_clock_inn/p) in case the PLL is bypassed.

Figure 16. Power Up Sequence

reset_n

vdd_18

vdd_33

clock input

vdd_pix

> 10us> 10us> 10us > 10us

SPI Upload

> 10us

Enable Clock Management − Part 1

The ‘Enable Clock Management’ action configures the

clock management blocks and activates the clock generation

and distribution circuits in a pre−defined way. First, a set of

clock settings must be uploaded through the SPI register.

These settings are dependent on the desired operation mode

of the sensor.

Table 6 shows the SPI uploads to be executed to configure

the sensor for P1−SN/SE/FN, P3−SN/SE 10−bit serial

mode, with the PLL, and all available LVDS channels.

Note that the SPI uploads to be executed to configure the

sensor for other supported modes (P1−SN/SE/FN 8−bit

serial,...) are available to customers under NDA at the

ON Semiconductor Image Sensor Portal

If the PLL is not used, the LVDS clock input must be

running.

It is important to follow the upload sequence listed in

Table 6.

Use of Phase Locked Loop

If PLL is used, the PLL is started after the upload of the

SPI registers. The PLL requires (dependent on the settings)

some time to generate a stable output clock. A lock detect

circuit detects if the clock is stable. When complete, this is

flagged in a status register.

Check the PLL_lock flag 24[0] by reading the SPI

Management− Part 2’ action can be continued. When PLL

is not used, this step can be bypassed as shown in Figure 15

on page 14.

NOIP1SN5000A

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Table 6. ENABLE CLOCK MANAGEMENT REGISTER UPLOAD − PART 1

Upload # Address Data Description

P1−SN/SE/FN, P3−SN/SE 10−bit mode with PLL

0x0000 Monochrome sensor

0x0001 Color sensor

2 32

0x7004 Configure clock management P1−SN/SE/FN only

0x7014 Configure clock management P3−SN/SE only

3 20 0x0000 Configure clock management

4 17 0x2113 Configure PLL

5 26 0x2280 Configure PLL lock detector

6 27 0x3D2D Configure PLL lock detector

7 8 0x0000 Release PLL soft reset

8 16 0x0003 Enable PLL

Enable Clock Management − Part 2

The next step to configure the clock management consists

of SPI uploads which enables all internal clock distribution.

The required uploads are listed in Table 7. Note that it is

important to follow the upload sequence listed in Table 7.

Table 7. ENABLE CLOCK MANAGEMENT REGISTER UPLOAD − PART 2

Upload # Address Data Description

P1−SN/SE/FN, P3−SN/SE 10−bit mode with PLL

9 0x0000 Release clock generator soft reset

2 32

0x7006 Enable logic clock for P1−SN/SE/FN only

0x7016 Enable logic clock for P3−SN/SE only

3 34 0x0001 Enable logic block

Required Register Upload

In this phase, the ‘reserved’ register settings are uploaded

through the SPI register. Different settings are not allowed

and may cause the sensor to malfunction. The required

uploads are listed in Table 8.

Table 8. REQUIRED REGISTER UPLOADS

Up-

load #

Ad-

dress

P1−SN/SE/FN 10−bit

mode with PLL

(8 LVDS NZROT)

P3−SN/SE 10−bit

mode with PLL

(4 LVDS NZROT)

1 41 0x0854 0x0854

2 42 0x0200 0x0200

3 43 0x000C 0x000C

4 65 0x48CB 0x48CB

5 66 0x53C8 0x53C4

6 67 0x8688 0x4544

7 68 0x0085 0x0085

8 69 0x0888 0x0848

9 70 0x4411 0x4411

10 71 0x9788 0x9788

11 72 0x3330 0x3330

12 128 0x4714 0x4714

13 129 0x8001 0x8001

14 171 0x1002 0x1002

15 175 0x0080 0x0080

16 176 0x00E6 0x00E6

17 177 0x0400 0x0400

18 192 0x000C 0x000C

19 193 0x4E00 0x2C00

20 194 0x02E4 0x02E4

21 197 0x0104 0x0104

22 199 0x0196 0x0174

23 200 0x0804 0x0804

24 201 0x00B1 0x0060

25 204 0x01E1 0x01E1

26 207 0x0000 0x0000

27 208 0xA100 0xA100

28 211 0x0E49 0x0E39

29 215 0x111F 0x111F

30 216 0x7F00 0x7F00

31 219 0x0020 0x0020

32 220 0x2434 0x2432

33 224 0x3E17 0x3E17

剩余80页未读，继续阅读

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