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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PM_EXTTS#0
V_DDR_MCH_REF
H_RCOMP
CLKREQ#_7
+H_SWNG
H_D#32
H_D#24
H_D#19
H_D#59
H_D#42
H_D#36
H_D#3
H_D#40
H_RCOMP
H_D#55
H_D#4
H_D#60
H_D#30
H_D#34
H_D#27
H_D#1
H_D#23
H_D#51
H_D#48
H_D#46
H_D#44
H_D#39
H_D#22
H_D#15
H_D#14
H_D#9
H_D#56
H_D#54
H_D#8
H_RESET#
H_D#37
H_D#35
H_D#28
H_D#25
H_D#12
H_D#38
H_D#26
H_D#11
H_D#7
H_D#53
H_D#52
H_D#41
H_D#18
H_D#10
+H_VREF
H_D#57
H_D#33
H_D#29
+H_SWNG
H_D#6
H_D#45
H_D#43
H_D#20
H_D#61
H_D#17
H_D#63
H_D#58
H_D#21
H_D#16
H_D#50
H_CPUSLP#
H_D#62
H_D#5
H_D#49
H_D#31
H_D#2
H_D#47
H_D#13
H_D#0
H_A#7
H_A#12
H_A#32
H_A#24
H_A#3
H_A#18
H_A#21
H_A#16
H_A#19
H_A#31
H_A#27
H_A#5
H_A#30
H_A#9
H_A#26
H_A#14
H_A#11
H_A#22
H_A#23
H_A#34
H_A#20
H_A#8
H_A#15
H_A#6
H_A#25
H_A#17
H_A#4
H_A#13
H_A#33
H_A#29
H_A#28
H_A#10
H_A#35
CLK_MCH_BCLK#
H_LOCK#
CLK_MCH_BCLK
H_ADSTB#1
H_DEFER#
H_HITM#
H_ADS#
H_BR0#
H_DBSY#
H_HIT#
H_BPRI#
H_DRDY#
H_BNR#
H_DPWR#
H_ADSTB#0
H_TRDY#
+H_VREF
H_DINV#0
H_DINV#3
H_DINV#1
H_DINV#2
H_DSTBN#1
H_DSTBN#3
H_DSTBN#0
H_DSTBN#2
H_DSTBP#2
H_DSTBP#0
H_DSTBP#3
H_DSTBP#1
H_REQ#0
H_REQ#3
H_REQ#1
H_REQ#4
H_REQ#2
H_RS#1
H_RS#0
H_RS#2
MCH_CLKSEL0
SMRCOMP_VOL
+CL_VREF
HDA_SDIN2_NB
MCH_ICH_SYNC#
CLKREQ#_7
CL_CLK0
CL_DATA0
CL_RST#
M_PWROK
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
MCH_SSCDREFCLK
MCH_SSCDREFCLK#
CLK_MCH_DREFCLK#
CLK_MCH_DREFCLK
CLK_MCH_3GPLL#
CLK_MCH_3GPLL
SM_PWROK
TP_SM_DRAMRST#
SM_REXT
V_DDR_MCH_REF
M_CLK_DDR3
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
M_CLK_DDR2
M_CLK_DDR0
M_CLK_DDR1
SMRCOMP_VOH
SMRCOMP_VOL
M_ODT1
SMRCOMP#
M_ODT3
M_ODT0
M_ODT2
SMRCOMP
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE3_DIMMB
DDR_CS1_DIMMA#
DDR_CKE2_DIMMB
DDR_CS0_DIMMA#
DDR_CS3_DIMMB#
DDR_CS2_DIMMB#
HDMICLK_NB
HDMIDAT_NB
MCH_CLKSEL1
MCH_CLKSEL2
CFG11
CFG9
CFG7
CFG10
CFG6
CFG14
CFG16
CFG15
CFG17
CFG8
CFG5
CFG13
CFG18
CFG19
CFG12
CFG20
H_DPRSTP#
THERMTRIP#
PM_PWROK
PM_EXTTS#1
PM_EXTTS#0
PM_BMBUSY#
DPRSLPVR
SMRCOMP_VOH
PLT_RST#
PM_EXTTS#1
TSATN#
H_D#[0..63]7
H_CPUSLP#7
H_RESET#6
H_A#[3..35] 6
H_ADS# 6
H_ADSTB#1 6
H_ADSTB#0 6
H_BPRI# 6
H_BNR# 6
H_DEFER# 6
H_BR0# 6
H_DBSY# 6
CLK_MCH_BCLK 17
CLK_MCH_BCLK# 17
H_DPWR# 7
H_DRDY# 6
H_HIT# 6
H_HITM# 6
H_LOCK# 6
H_TRDY# 6
H_DINV#0 7
H_DINV#1 7
H_DINV#2 7
H_DINV#3 7
H_DSTBN#0 7
H_DSTBN#1 7
H_DSTBN#2 7
H_DSTBN#3 7
H_DSTBP#0 7
H_DSTBP#1 7
H_DSTBP#2 7
H_DSTBP#3 7
H_REQ#3 6
H_REQ#2 6
H_REQ#1 6
H_REQ#4 6
H_REQ#0 6
H_RS#2 6
H_RS#1 6
H_RS#0 6
MCH_CLKSEL017
MCH_CLKSEL117
MCH_CLKSEL217
TSATN# 32
HDA_RST#_NB 21
HDA_SYNC_NB 21
HDA_SDOUT_NB 21
MCH_ICH_SYNC# 22
CL_CLK0 22
CL_DATA0 22
M_PWROK 22,32
CL_RST# 22
DMI_TXP0 22
DMI_RXN0 22
DMI_RXP0 22
DMI_TXN0 22
DMI_TXN1 22
DMI_TXN2 22
DMI_TXN3 22
DMI_TXP1 22
DMI_TXP2 22
DMI_TXP3 22
DMI_RXN1 22
DMI_RXN2 22
DMI_RXN3 22
DMI_RXP1 22
DMI_RXP2 22
DMI_RXP3 22
CLK_MCH_3GPLL 17
CLK_MCH_3GPLL# 17
MCH_SSCDREFCLK 17
MCH_SSCDREFCLK# 17
CLK_MCH_DREFCLK 17
CLK_MCH_DREFCLK# 17
DDR_CKE0_DIMMA 15
DDR_CKE1_DIMMA 15
DDR_CKE2_DIMMB 16
DDR_CKE3_DIMMB 16
DDR_CS0_DIMMA# 15
DDR_CS1_DIMMA# 15
DDR_CS2_DIMMB# 16
DDR_CS3_DIMMB# 16
M_CLK_DDR0 15
M_CLK_DDR1 15
M_CLK_DDR2 16
M_CLK_DDR3 16
M_CLK_DDR#0 15
M_CLK_DDR#1 15
M_CLK_DDR#2 16
M_CLK_DDR#3 16
M_ODT0 15
M_ODT1 15
M_ODT2 16
M_ODT3 16
HDMIDAT_NB 34
HDMICLK_NB 34
CLKREQ#_7 17
CFG511
CFG911
CFG1111
CFG1011
CFG611
CFG711
CFG1311
CFG1211
CFG1611
CFG1811
CFG2011
CFG1911
CFG811
CFG1411
CFG1511
CFG1711
PM_BMBUSY#22
H_DPRSTP#7,21,42
PM_EXTTS#015
DPRSLPVR22,42
PM_EXTTS#116
PM_PWROK22,32
H_THERMTRIP#6,21
PLT_RST#20,25,26
HDA_BITCLK_NB 21
HDA_SDIN2 21
V_DDR_MCH_REF15,16
+VCCP
+VCCP
+3VS
+1.8V
+1.8V
+VCCP
+1.8V
+VCCP
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Montevina UMA
0.1
Cantiga(1/6)-AGTL/DMI/DDR
Custom
9 46Wednesday, February 18, 2009
2007/08/28 2006/03/10
Compal Electronics, Inc.
Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20
Layout Note: V_DDR_MCH_REF
trace width and spacing is 20/20.
Near B3 pinwithin 100 mils from NB
Layout note:
Route H_SCOMP and H_SCOMP# with trace
width, spacing and impedance (55 ohm) same as
FSB data traces
0621 add CLK and DAT for DVI
0830 Add pull-up and pull-down resistor.
*R44*Follow
Intel feedback
Follow Design Guide
For Cantiga: 80.6ohm
80% of 1.8V VCC_SM
20% of 1.8V VCC_SM
+V_DDR_MCH_REF generated by DC-DC
T19
T7
R44
499_0402_1%
12
R52
2K_0402_1%
12
R35 80.6_0402_1%
1 2
T28
T26
R737 56_0402_5%
1 2
T30
R40 10K_0402_5%
1 2
T11
C53
2.2U_0603_6.3V4Z
1
2
R36 0_0402_5%
1 2
T35
T25
R41
100_0402_5%
1 2
T18
T37
T86
R46
1K_0402_1%
12
C52
0.01U_0402_25V7K
1
2
T10
C54
0.01U_0402_25V7K
1
2
T20
R54
24.9_0402_1%
12
T17
R48
10K_0402_1%
12
T85
R42
0_0402_5%
1 2
T29
R39 10K_0402_5%
1 2
PM
MISC
NC
DDR CLK/ CONTROL/COMPENSATION
CLK
DMI
CFG
RSVD
GRAPHICS VID
MEHDA
U2B
CANTIGA ES_FCBGA1329
SA_CK_0
AP24
SA_CK_1
AT21
SB_CK_0
AV24
SA_CK#_0
AR24
SA_CK#_1
AR21
SB_CK#_0
AU24
SA_CKE_0
BC28
SA_CKE_1
AY28
SB_CKE_0
AY36
SB_CKE_1
BB36
SA_CS#_0
BA17
SA_CS#_1
AY16
SB_CS#_0
AV16
SB_CS#_1
AR13
SM_DRAMRST#
BC36
SA_ODT_0
BD17
SA_ODT_1
AY17
SB_ODT_0
BF15
SB_ODT_1
AY13
SM_RCOMP
BG22
SM_RCOMP#
BH21
CFG_18
P29
CFG_19
R28
CFG_2
P25
CFG_0
T25
CFG_1
R25
CFG_20
T28
CFG_3
P20
CFG_4
P24
CFG_5
C25
CFG_6
N24
CFG_7
M24
CFG_8
E21
CFG_9
C23
CFG_10
C24
CFG_11
N21
CFG_12
P21
CFG_13
T21
CFG_14
R20
CFG_15
M20
CFG_16
L21
CFG_17
H21
PM_SYNC#
R29
PM_EXT_TS#_0
N33
PM_EXT_TS#_1
P32
PWROK
AT40
RSTIN#
AT11
DPLL_REF_CLK
B38
DPLL_REF_CLK#
A38
DPLL_REF_SSCLK
E41
DPLL_REF_SSCLK#
F41
DMI_RXN_0
AE41
DMI_RXN_1
AE37
DMI_RXN_2
AE47
DMI_RXN_3
AH39
DMI_RXP_0
AE40
DMI_RXP_1
AE38
DMI_RXP_2
AE48
DMI_RXP_3
AH40
DMI_TXN_0
AE35
DMI_TXN_1
AE43
DMI_TXN_2
AE46
DMI_TXN_3
AH42
DMI_TXP_0
AD35
DMI_TXP_1
AE44
DMI_TXP_2
AF46
DMI_TXP_3
AH43
RESERVED
AL34
RESERVED
AN35
RESERVED
AK34
RESERVED
AM35
RESERVED
BG23
RESERVED
BF23
RESERVED
BH18
RESERVED
BF18
PM_DPRSTP#
B7
SB_CK_1
AU20
SB_CK#_1
AV20
RESERVED
AY21
RESERVED
AH9
RESERVED
AH10
RESERVED
AH12
RESERVED
AH13
RESERVED
M36
RESERVED
N36
RESERVED
R33
RESERVED
T33
GFX_VID_0
B33
GFX_VID_1
B32
GFX_VID_2
G33
GFX_VID_3
F33
GFX_VR_EN
C34
SM_RCOMP_VOH
BF28
SM_RCOMP_VOL
BH28
THERMTRIP#
T20
DPRSLPVR
R32
RESERVED
K12
CL_CLK
AH37
CL_DATA
AH36
CL_PWROK
AN36
CL_RST#
AJ35
CL_VREF
AH34
NC
A47
NC
BG48
NC
BF48
NC
BD48
NC
BC48
NC
BH47
NC
BG47
NC
BE47
NC
BH46
NC
BF46
NC
BG45
NC
BH44
NC
BH43
NC
BH6
NC
BH5
NC
BG4
SDVO_CTRLCLK
G36
SDVO_CTRLDATA
E36
CLKREQ#
K36
RESERVED
T24
ICH_SYNC#
H36
TSATN#
B12
PEG_CLK#
E43
PEG_CLK
F43
NC
BH3
GFX_VID_4
E33
RESERVED
B31
DDPC_CTRLCLK
N28
NC
BF3
NC
BH2
NC
BG2
NC
BE2
NC
BG1
NC
BF1
NC
BD1
NC
BC1
NC
F1
SM_VREF
AV42
SM_PWROK
AR36
SM_REXT
BF17
RESERVED
M1
HDA_BCLK
B28
HDA_RST#
B30
HDA_SDI
B29
HDA_SDO
C29
HDA_SYNC
A28
DDPC_CTRLDATA
M28
RESERVED
B2
T13
C59
0.1U_0402_16V4Z
1
2
R45
10K_0402_1%
12
C58
0.1U_0402_16V4Z
1
2
T12
T31
R37 499_0402_1%
1 2
T23
T22
T27
T15
R43
1K_0402_1%
12
R210
33_0402_5%
1 2
R34 80.6_0402_1%
1 2
R31
1K_0402_1%
12
T14
T36
R47
221_0603_1%
12
C56
0.1U_0402_16V4Z
1
2
C51
2.2U_0603_6.3V4Z
1
2
R33
1K_0402_1%
12
T16
C57
0.1U_0402_16V4Z
1
2
T24
HOST
U2A
CANTIGA ES_FCBGA1329
H_A#_10
P16
H_A#_11
R16
H_A#_12
N17
H_A#_13
M13
H_A#_14
E17
H_A#_15
P17
H_A#_16
F17
H_A#_17
G20
H_A#_18
B19
H_A#_19
J16
H_A#_20
E20
H_A#_21
H16
H_A#_22
J20
H_A#_23
L17
H_A#_24
A17
H_A#_25
B17
H_A#_26
L16
H_A#_27
C21
H_A#_28
J17
H_A#_29
H20
H_A#_3
A14
H_A#_30
B18
H_A#_31
K17
H_A#_4
C15
H_A#_5
F16
H_A#_6
H13
H_A#_7
C18
H_A#_8
M16
H_A#_9
J13
H_ADS#
H12
H_ADSTB#_0
B16
H_ADSTB#_1
G17
H_BNR#
A9
H_BPRI#
F11
H_BREQ#
G12
HPLL_CLK#
AH6
H_CPURST#
C12
HPLL_CLK
AH7
H_D#_0
F2
H_REQ#_2
F13
H_REQ#_3
B13
H_D#_1
G8
H_D#_10
M9
H_D#_20
L6
H_D#_30
N10
H_D#_40
AA8
H_D#_50
AA2
H_D#_60
AE11
H_D#_8
D4
H_D#_9
H3
H_DBSY#
B10
H_D#_11
M11
H_D#_12
J1
H_D#_13
J2
H_D#_14
N12
H_D#_15
J6
H_D#_16
P2
H_D#_17
L2
H_D#_18
R2
H_D#_19
N9
H_D#_2
F8
H_D#_21
M5
H_D#_22
J3
H_D#_23
N2
H_D#_24
R1
H_D#_25
N5
H_D#_26
N6
H_D#_27
P13
H_D#_28
N8
H_D#_29
L7
H_D#_3
E6
H_D#_31
M3
H_D#_32
Y3
H_D#_33
AD14
H_D#_34
Y6
H_D#_35
Y10
H_D#_36
Y12
H_D#_37
Y14
H_D#_38
Y7
H_D#_39
W2
H_D#_4
G2
H_D#_41
Y9
H_D#_42
AA13
H_D#_43
AA9
H_D#_44
AA11
H_D#_45
AD11
H_D#_46
AD10
H_D#_47
AD13
H_D#_48
AE12
H_D#_49
AE9
H_D#_5
H6
H_D#_51
AD8
H_D#_52
AA3
H_D#_53
AD3
H_D#_54
AD7
H_D#_55
AE14
H_D#_56
AF3
H_D#_57
AC1
H_D#_58
AE3
H_D#_59
AC3
H_D#_6
H2
H_D#_61
AE8
H_D#_62
AG2
H_D#_63
AD6
H_D#_7
F6
H_DEFER#
E9
H_DINV#_0
J8
H_DINV#_1
L3
H_DINV#_2
Y13
H_DINV#_3
Y1
H_DPWR#
J11
H_DRDY#
F9
H_DSTBN#_0
L10
H_DSTBN#_1
M7
H_DSTBN#_2
AA5
H_DSTBN#_3
AE6
H_DSTBP#_0
L9
H_DSTBP#_1
M8
H_DSTBP#_2
AA6
H_DSTBP#_3
AE5
H_AVREF
A11
H_DVREF
B11
H_TRDY#
C9
H_HIT#
H9
H_HITM#
E12
H_LOCK#
H11
H_REQ#_0
B15
H_REQ#_1
K13
H_REQ#_4
B14
H_A#_32
B20
H_A#_33
F21
H_A#_34
K21
H_A#_35
L20
H_SWING
C5
H_CPUSLP#
E11
H_RCOMP
E3
H_RS#_0
B6
H_RS#_1
F12
H_RS#_2
C8
R32
3.01K_0402_1%
12
C55
0.1U_0402_16V4Z
@
1
2
R55
100_0402_1%
12
T8
R38 10K_0402_5%
1 2
T9