FT2232H：全能USB转UART/FIFO接口芯片手册

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FT2232H是一款由Future Technology Devices International Limited（FTDI）生产的第五代高速USB接口芯片，专为将USB 2.0（高达480 Mb/s）信号转换成多种工业标准串行或并行接口而设计。该文档是FT2232H的详细数据手册，版本为2.6，编号为FT_000061，经过了FTDI的第77号批准。这款芯片的独特之处在于其集成性强大，能够在单个芯片上实现两个USB接口与两个独立的串行/并行端口之间的通信。这意味着用户无需进行复杂的USB特定固件编程，就能轻松地在硬件层面处理USB协议，大大简化了系统设计过程。 FT2232H兼容USB 2.0的High Speed模式（480 Mbits/秒）和Full Speed模式（12 Mbits/秒），提供了灵活性，可以根据应用需求选择合适的传输速率。其内置的双多协议同步串行引擎（MPSSE）进一步简化了对同步串行协议（如USB到JTAG、I2C、SPI等）的支持，使得开发者能够轻松应对各种接口标准。此外，FT2232H拥有两个独立的工作模式，既可以作为通用异步接收器/发送器（UART）进行串行通信，也可以作为先进功能接口（FIFO）或MPSSE，提供高效的数据缓冲和处理能力。每个端口都配备有独立的波特率发生器，允许用户灵活设置各个接口的通信速率。对于串行通信，包括RS232、RS422和RS485标准，FT2232H支持的数据传输速率高达12 Mbaud，但实际传输速率可能会受到外部线路条件的限制。这表明它在工业级通信中具有广泛的应用潜力，特别适合那些需要高性能、多功能接口转换的场合，如嵌入式系统开发、电子测试设备和物联网应用等。 FT2232H凭借其卓越的性能、高度的灵活性和易于集成的特性，成为现代电子设计中不可或缺的组件，能显著提升系统的效率和可靠性。设计者在利用此芯片时，应充分了解其特性和配置选项，以便最大化其实用价值。

FT2232H Dual High Speed USB to Multipurpose UART/FIFO IC Datasheet

Version 2.6

Document No.: FT_000061 Clearance No.: FTDI#77

24,23,22,

21,

19,18,17,

ADBUS[7:0]

I/O

D7 to D0 bidirectional FIFO data. This bus is normally input

unless OE# is low.

RXF#

OUTPUT

When high, do not read data from the FIFO. When low, there

is data available in the FIFO which can be read by driving RD#

low. When in synchronous mode, data is transferred on every

clock that RXF# and RD# are both low. Note that the OE# pin

must be driven low at least 1 clock period before asserting

RD# low.

TXE#

OUTPUT

When high, do not write data into the FIFO. When low, data

can be written into the FIFO by driving WR# low. When in

synchronous mode, data is transferred on every clock that

TXE# and WR# are both low.

RD#

INPUT

Enables the current FIFO data byte to be driven onto D0...D7

when RD# goes low. The next FIFO data byte (if available) is

fetched from the receive FIFO buffer each CLKOUT cycle until

RD# goes high.

WR#

INPUT

Enables the data byte on the D0...D7 pins to be written into

the transmit FIFO buffer when WR# is low. The next FIFO

data byte is written to the transmit FIFO buffer each CLKOUT

cycle until WR# goes high.

CLKOUT

OUTPUT

60 MHz Clock driven from the chip. All signals should be

synchronized to this clock.

OE#

INPUT

Output enable when low to drive data onto D0-7. This should

be driven low at least 1 clock period before driving RD# low to

allow for data buffer turn-around.

SIWU

INPUT

The Send Immediate / WakeUp signal combines two functions

on a single pin. If USB is in suspend mode (PWREN# = 1) and

remote wakeup is enabled in the EEPROM, strobing this pin

low will cause the device to request a resume on the USB Bus.

Normally, this can be used to wake up the Host PC.

During normal operation (PWREN# = 0), if this pin is strobed

low any data in the device TX buffer will be sent out over USB

on the next Bulk-IN request from the drivers regardless of the

pending packet size. This can be used to optimize USB

transfer speed for some applications. Tie this pin to VCCIO if

not used. (Also see note 1, 2, 3 in section Error! Reference

source not found.)

Table 3.6 Channel A FT245 Style Synchronous FIFO Configured Pin Descriptions

For a functional description of this mode, please refer to section 4.4.

3.1.4.3 FT2232H pins used in an FT245 Style Asynchronous FIFO Interface

The FT2232H channel A or channel B can be configured as a FT245 asynchronous FIFO interface. When

configured in this mode, the pins used and the descriptions of the signals are shown in Table 3.7. To

enter this mode the external EEPROM must be set to make port A or B or both 245 mode. In this mode,

data is written or read on the falling edge of the RD# or WR# signals.

Channel A

Pin No.

Channel B

Pin No.

Name

Type

FT245 Configuration Description

24,23,22,21,

19,18,17,16

46,45,44,43,

41,40,39,38

Channel A =

ADBUS[7:0]

Channel B =

BDBUS[7:0]

I/O

D7 to D0 bidirectional FIFO data. This bus is

normally input unless RD# is low.

RXF#

OUTPUT

When high, do not read data from the FIFO.

When low, there is data available in the FIFO

which can be read by driving RD# low. When

RD# goes high again RXF# will always go

high and only become low again if there is

another byte to read. During reset this signal

FT2232H Dual High Speed USB to Multipurpose UART/FIFO IC Datasheet

Version 2.6

Document No.: FT_000061 Clearance No.: FTDI#77

pin is tri-state, but pulled up to VCCIO via an

internal 200kΩ resistor.

TXE#

OUTPUT

When high, do not write data into the FIFO.

When low, data can be written into the FIFO

by strobing WR# high, then low. During reset

this signal pin is tri-state, but pulled up to

VCCIO via an internal 200kΩ resistor.

RD#

INPUT

Enables the current FIFO data byte to be

driven onto D0...D7 when RD# goes low.

Fetches the next FIFO data byte (if available)

from the receive FIFO buffer when RD# goes

high.

WR#

INPUT

Writes the data byte on the D0...D7 pins into

the transmit FIFO buffer when WR# goes

from high to low.

SIWU

INPUT

The Send Immediate / WakeUp signal

combines two functions on a single pin. If

USB is in suspend mode (PWREN# = 1) and

remote wakeup is enabled in the EEPROM,

strobing this pin low will cause the device to

request a resume on the USB Bus. Normally,

this can be used to wake up the Host PC.

During normal operation (PWREN# = 0), if

this pin is strobed low any data in the device

TX buffer will be sent out over USB on the

next Bulk-IN request from the drivers

regardless of the pending packet size. This

can be used to optimize USB transfer speed

for some applications. Tie this pin to VCCIO if

not used. (Also see note 1, 2, 3 in section

Error! Reference source not found.)

Table 3.7 Channel A and Channel B FT245 Style Asynchronous FIFO Configured Pin

Descriptions

3.1.4.4 FT2232H pins used in a Synchronous or Asynchronous Bit-Bang Interface

The FT2232H channel A or channel B can be configured as a synchronous or asynchronous bit-bang

interface. Bit-bang mode is a special FTDI FT2232H device mode that changes the 8 IO lines on either (or

both) channels into an 8 bit bi-directional data bus. There are two types of bit-bang modes: synchronous

and asynchronous.

When configured in any bit-bang mode, the pins used and the descriptions of the signals are shown in

Table 3.8.

Channel A

Pin No.

Channel B

Pin No.

Name

Type

Configuration Description

24,23,22,21,

19,18,17,16

46,45,44,43,

41,40,39,38

Channel A =

ADBUS[7:0]

Channel B =

BDBUS[7:0]

I/O

D7 to D0 bidirectional Bit-Bang

parallel I/O data pins

WRSTB#

OUTPUT

Write strobe, active low output

indicates when new data has been

written to the I/O pins from the

Host PC (via the USB interface).

RDSTB#

OUTPUT

Read strobe, this output rising

edge indicates when data has

been read from the parallel I/O

pins and sent to the Host PC (via

the USB interface).

SIWU

INPUT

The Send Immediate / WakeUp

signal combines two functions on a

single pin. If USB is in suspend

mode (PWREN# = 1) and remote

FT2232H Dual High Speed USB to Multipurpose UART/FIFO IC Datasheet

Version 2.6

Document No.: FT_000061 Clearance No.: FTDI#77

wakeup is enabled in the EEPROM,

strobing this pin low will cause the

device to request a resume on the

USB Bus. Normally, this can be

used to wake up the Host PC.

During normal operation (PWREN#

= 0), if this pin is strobed low any

data in the device TX buffer will be

sent out over USB on the next

Bulk-IN request from the drivers

regardless of the pending packet

size. This can be used to optimize

USB transfer speed for some

applications. Tie this pin to VCCIO

if not used. (Also see note 1, 2, 3

in section Error! Reference

source not found.)

Table 3.8 Channel A and Channel B Synchronous or Asynchronous Bit-Bang Configured Pin

Descriptions

For a functional description of this mode, please refer to section Error! Reference source not found.

Error! Reference source not found..

3.1.4.5 FT2232H pins used in an MPSSE

The FT2232H channel A and channel B, each have a Multi-Protocol Synchronous Serial Engine (MPSSE).

Each MPSSE can be independently configured to a number of industry standard serial interface protocols

such as JTAG, I2C or SPI, or it can be used to implement a proprietary bus protocol. For example, it is

possible to use one of the FT2232H’s channels to connect to an SRAM configurable FPGA such as supplied

by Altera or Xilinx. The FPGA device would normally be un-configured (i.e. have no defined function) at

power-up. Application software on the PC could use the MPSSE to download configuration data to the

FPGA over USB. This data would define the hardware function on power up. The other FT2232H channel

would be available for another function. Alternatively each MPSSE can be used to control a number of

GPIO pins. When configured in this mode, the pins used and the descriptions of the signals are shown

Table 3.9.

Channel

Pin No.

Channel B

Pin No.

Name

Type

MPSSE Configuration Description

TCK/SK

OUTPUT

Clock Signal Output. For example:

JTAG – TCK, Test interface clock

SPI – SK, Serial Clock

TDI/DO

OUTPUT

Serial Data Output. For example:

JTAG – TDI, Test Data Input

SPI – DO

TDO/DI

INPUT

Serial Data Input. For example:

JTAG – TDO, Test Data output

SPI – DI, Serial Data Input

TMS/CS

OUTPUT

Output Signal Select. For example:

JTAG – TMS, Test Mode Select

SPI – CS, Serial Chip Select

GPIOL0

I/O

General Purpose input/output

GPIOL1

I/O

General Purpose input/output

GPIOL2

I/O

General Purpose input/output

GPIOL3

I/O

General Purpose input/output

GPIOH0

I/O

General Purpose input/output

GPIOH1

I/O

General Purpose input/output

GPIOH2

I/O

General Purpose input/output

GPIOH3

I/O

General Purpose input/output

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