List of TablesBCM5396 Data Sheet
Broadcom
®
Single-Chip 16-Port SerDes Gigabit Switch
June 20, 2016 • 5396-DS116-R Page 20
Table 110: PRBS Status Register (Page 10h ~ 1Fh: Address 32h ~ 33h) .................................................... 142
Table 111: Pattern Generator Control Register (Page 10h ~ 1Fh: Address 34h ~ 35h)................................ 142
Table 112: Pattern Generator Control Register (Page 10h ~ 1Fh: Address 36h ~ 37h)................................ 143
Table 113: Pattern Generator Control Register (Page 10h ~ 1Fh: Address 36h ~ 37h)................................ 144
Table 114: Force Transmit 1 Register (Page 10h ~ 1Fh: Address 3Ah ~ 3Bh) ............................................. 144
Table 115: Block Address (Pages 10h–1Fh: Address 3Eh ~ 3Fh) ................................................................ 144
Table 116: QoS Registers (Page 30h) ........................................................................................................... 145
Table 117: QoS Global Control Register (Page 30h: Address 00h) .............................................................. 146
Table 118: QoS Threshold Control Register (Page 30h: Address 01h–02h)................................................. 147
Table 119: QoS 1P Enable Register (Page 30h: Address 04h–07h)............................................................. 147
Table 120: QoS DiffServ Enable Register (Page 30h: Address 08h–0Bh) .................................................... 147
Table 121: 1P/1Q Priority Map Register (Page 30h: Address 10h–13h) ....................................................... 147
Table 122: DiffServ Priority Map 0 Register (Page 30h: Address 30h–35h).................................................. 148
Table 123: DiffServ Priority Map 1 Register (Page 30h: Address 36h–3Bh) ................................................. 149
Table 124: DiffServ Priority Map 2 Register (Page 30h: Address 3Ch–41h) ................................................. 150
Table 125: DiffServ Priority Map 3 Register (Page 30h: Address 42h–47h).................................................. 150
Table 126: QoS Port Control N Register (Page 30h: Address 50h–71h)....................................................... 151
Table 127: QoS TX Control Register (Page 30h: Address 80h) .................................................................... 152
Table 128: Queue N Weight Register (Page 30h: Address 81h–84h) ........................................................... 152
Table 129: EtherType Priority Control Register (Page 30h: Address 88h–8Bh)............................................ 153
Table 130: Enable Traffic Priority Remap Control Register (Page 30h: Address A0h–A3h) ......................... 153
Table 131: Traffic Priority Remap Register (Page 30h: Address A4h) .......................................................... 153
Table 132: Page 31h Port-based VLAN Registers ........................................................................................ 154
Table 133: Port VLAN Control Register (Pages: 31h, Address 0h–43h) ....................................................... 154
Table 134: Trunking Registers (Page 32h) .................................................................................................... 154
Table 135: MAC Trunk Control Register (Pages: 32h, Address 1h) .............................................................. 156
Table 136: Trunk Group Register [0:3] (Pages: 32h, Address 90h–9Fh) ...................................................... 157
Table 137: QoS Registers (Page 34h) ........................................................................................................... 158
Table 138: Global Control 0 Register (Pages 34h: Address 00h).................................................................. 158
Table 139: Global Control 1 Register (Pages 34h: Address 01h).................................................................. 159
Table 140: Global Control 2 Register (Pages 34h: Address 02h).................................................................. 160
Table 141: Global Control 3 Register (Pages 34h: Address 03h–06h).......................................................... 160
Table 142: Global Control 4 Register (Pages 34: Address 07h) .................................................................... 160
Table 143: Global Control 5 Register (Pages 34h: Address 08h).................................................................. 161
Table 144: New Priority Map Register (Pages 34h: Address 0C–0Fh).......................................................... 162
Table 145: Port N Default 802.1Q Tag Register (Pages 34h: Address 10h–31h) ......................................... 162
Table 146: Jumbo Frame Control Registers (Page 40h) ............................................................................... 163