Future Generation Computer Systems 93 (2019) 58–67
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Future Generation Computer Systems
journal homepage: www.elsevier.com/locate/fgcs
Lifetime-aware FTL to improve the lifetime and performance of
solid-state drives
Yubiao Pan
a,b,
∗
, Yongkun Li
c
, Huizhen Zhang
a
, Yinlong Xu
c
a
The School of Computer Science and Technology, Huaqiao university, Xiamen, China
b
The College of Mechanical Engineering and Automation, Huaqiao university, Xiamen, China
c
The School of Computer Science and Technology, University of Science and Technology of China, Hefei, China
h i g h l i g h t s
• A compression-aware PMT achieves less memory cost compared with existing schemes.
• A latency-aware read approach is proposed to address the read amplification problem.
• A latency-aware write approach is proposed to further improve the performance.
a r t i c l e i n f o
Article history:
Received 9 January 2018
Accepted 7 October 2018
Available online xxxx
Keywords:
Solid-state drives
Lifetime-aware FTL
Compression
Endurance
Performance
a b s t r a c t
Data compression techniques have been deployed in SSDs to prolong their lifetime due to the good trade-
off between data reduction and performance degradation. However, existing schemes either consume
plenty of DRAM resources, or cause the read amplification problem, which may further result in significant
performance degradation. In this paper, we propose a lifetime-aware FTL scheme (LAFTL) to improve
both the lifetime and performance of SSDs by compressing several pages into one physical page. We then
design a compression-aware page mapping table (PMT) to reduce the memory consumption, and propose
a latency-aware approach to improve the performance. We conduct extensive trace-driven evaluations
based on real-world workloads, and results show that our LAFTL reduces the average response time of
reads by 3%–78% and ensures a minimal resource consumption in DRAM while obtaining an acceptable
data reduction rate compared to other schemes.
© 2018 Elsevier B.V. All rights reserved.
1. Introduction
Flash-based solid-state drives (SSDs) are a type of emerging
storage devices which provide higher I/O performance, lower
power consumption and less noise than traditional HDDs. As the
price of SSDs continues to drop, SSDs have been widely deployed
in consumer devices, desktop systems and large scale storage
systems [1–3].
However, SSDs have several limitations, one major issue is that
each block in an SSD will wear out after a limited number of
program/erase cycles. For example, multi-level cell (MLC) SSDs
allow a block to support only 10K erasures, and this number may
even drop down to several thousand for triple-level cell (TLC)
SSDs [4,5]. When a block reaches its limited number of erasures,
it will be treated as a bad block and replaced by a new block in
the over-provisioning area, which has a limited size. On the other
∗
Correspondence to: The School of Computer Science and Technology, Huaqiao
University, No. 668, Jimei Road, Jimei District, Xiamen City, Fujian Province, China.
E-mail addresses: panyubiao@hqu.edu.cn (Y. Pan), ykli@ustc.edu.cn (Y. Li),
zhanghz@hqu.edu.cn (H. Zhang), ylxu@ustc.edu.cn (Y. Xu).
hand, bit error rate in flash chip increases as SSDs undergo more
erasures [6,7], and the increase will become sharp as the number
of erasures reach the limit.
Since less data written into SSDs may lead to less erasures,
data reduction technologies provide a good choice to prolong the
lifetime of SSDs. For example, data compression schemes have
been developed in SSDs [8–12]. Existing data compression schemes
are all deployed in the FTL and they can be classified into three
categories: compression packing [8–10], combination compress-
ing [11], and compression compacting [12]. For ease of presenta-
tion, we denote the compression packing, the combination com-
pression and the compression compacting as CompPack, Comb-
Comp and CompComp, respectively. In particular, CompPack com-
presses each incoming page data first, then stores them in the
buffer, finally packs them into a single page. It needs an additional
structure to record offset and size of each compressed page in page
mapping table (PMT), which consumes a large amount of resources
of DRAM in SSDs. Besides, data reduction rate of CompPack is
also the lowest among the three schemes. CombComp combines
fixed-size group of incoming page data (e.g. 4 pages) into a chunk
in the buffer first, then compresses the chunk and flushes the
https://doi.org/10.1016/j.future.2018.10.011
0167-739X/© 2018 Elsevier B.V. All rights reserved.