STM32 ARM微控制器详解：工程师入门指南

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"The Insiders Guide to the STM32 ARM based Microcontroller Hitex .pdf" 本文档是"The Insider's Guide to the STM32 ARM Based Microcontroller"的指南，由Trevor Martin撰写，Hitex (UK) Ltd.出版，旨在向工程师介绍STM32系列微控制器。STM32是由意法半导体（STMicroelectronics）生产的基于ARM Cortex-M内核的微控制器系列。此书于2008年首次发布，内容涵盖了STM32的特性、安全性、软件开发等方面。 1. 引言作者在引言部分介绍了Cortex-M系列处理器的核心概念，这是STM32的基础。Cortex-M是ARM公司设计的一种低功耗、高性能的微控制器核心，适用于实时应用。 2. STM32简介 - 复杂性：STM32系列以其丰富的外设集和高集成度著称，包括多个定时器、串行通信接口、数字信号处理器功能等，这使得它能够处理各种复杂的嵌入式任务。 - 安全性：STM32具有多种安全特性，如独立看门狗、内存保护单元等，这些功能确保系统在异常情况下仍能稳定运行。 - 安全性：在数据保护方面，STM32提供了加密硬件加速器和安全存储区域，支持安全固件更新和防止未经授权的访问。 - 软件开发：STM32支持多种开发工具和生态系统，包括ST的STM32CubeMX配置工具和STM32CubeIDE，以及广泛的第三方库和框架，简化了开发者的工作。 - 性能线与访问线：STM32分为性能线和访问线两个产品线，性能线提供更高的处理速度和更强大的外设，而访问线则提供经济高效的解决方案，适合对成本敏感的应用。 3. Cortex-M处理器特点 Cortex-M系列处理器强调了易于使用的开发环境、高效能和低功耗。它们采用了thumb-2指令集，提高了代码密度，同时支持中断处理和实时响应，适合嵌入式系统的实时性需求。 4. STM32硬件特性 STM32微控制器通常包含高性能的浮点单元（FPU）、高速闪存、多种接口（如SPI、I2C、CAN、USB等）、模拟外设（ADC、DAC）和电源管理模块。这些特性使得STM32在物联网、工业自动化、消费电子等领域广泛应用。 5. 开发工具和调试文档可能会详细讨论如何使用IDE、编译器、调试器进行STM32应用程序的开发和调试，包括使用JTAG或SWD接口进行硬件调试，以及如何使用HAL（Hardware Abstraction Layer）库来简化编程。 6. 应用实例可能会提供一些实际应用示例，展示如何利用STM32的特性来解决特定问题，例如控制电机、实现无线通信或构建传感器网络。这份指南深入浅出地介绍了STM32微控制器的各个方面，对于想要理解和开发基于STM32的嵌入式系统的工程师来说，是一份宝贵的参考资料。

Chapter 2: Cortex Overview

Consequently all the program activity focuses around the CPU register file. This register file consists of sixteen

32-bit wide registers. Registers R0-R12 are simple registers that can be used to hold program variables. The

Registers R13-R15 have special functions within the Cortex CPU. Register R13 is used as the stack pointer. This

space. This is typically used by an RTOS which can run its ‘system’ code in a protected mode. In the Cortex CPU

the two stacks are called the main stack and the process stack. The next register R14 is called the link register.

This register is used to store the return address when a call is made to a procedure. This allows the Cortex CPU

to make a fast entry and exit to a procedure. If your code calls several levels of subroutines, the compiler will

automatically store R14 on the stack. The final register R15 is the program counter; since this is part of the central

2.3.2.1 XPSR

In addition to the register file there is a separate register called the Program Status Register. This is not part of

the main register file and is only accessible through two dedicated instructions. The xPSR contains a number of

fields that influence the execution of the Cortex CPU.

The xPSR register can also be accessed through three special alias names that allow access to sub-ranges of

bits within the xPSR. The top five bits are the condition code flags and are aliased as the Application Program

Status Register. The first four condition code flags N,Z,C,V ( Negative, Zero, Carry and Overflow) w i ll be set and

cleared depending on the result of a data processing instruction. The Q bit is used by the DPS saturated maths

instructions to indicate that a variable has reached its maximum or minimum value. Like the ARM 32-bit

instruction set, certain Thumb-2 instructions are only executed if the instruction condition code matches the state

of the Application Program Status Register flags. If the instruction condition codes do not match, the instruction

passes through the pipeline as a NOP. This ensures that instructions flow smoothly through the pipeline and

minimises pipeline flushes. In the Cortex CPU, this technique is extended with the Execution Program Status

The Cortex-M3 has a CPU register file of 16 32-bit wide registers. Like the

earlier ARM7/9 CPUs R13 is the stack pointer. R14 is the link register and

R15 is the PC. R13 is a banked register to allow the Cortex-M3 to operate

with two stacks: a process stack and a main stack.

The Program Status Register contains status fields for instruction execution. This register is

aliased into the Application, Execution and Interrupt Status Registers

Chapter 2: Cortex Overview

2.3.3 CPU Operating Modes

While the Cortex processor is designed to be a low gate count, fast and easy to use microcontroller core, it has

been designed to support the use of a real-time operating system. The Cortex processor has two operating

modes: Thread mode and Handler mode. The CPU will run in Thread mode while it is executing in non-interrupt

background mode and will switch to the Handler mode when it is executing exceptions. In addition, the Cortex

CPU can execute code in a privileged or non-privileged mode. In privileged mode, the CPU has access to the full

instruction set. In unprivileged mode certain instructions are disabled (such as the MRS and MSR instructions

which allow access to the xPSR and its aliases). Additionally, access to most registers in the Cortex processor

system control space is also disabled. Stack usage can also be configured. The main stack (R13) can be used by

both Thread and Handler mode. Alternatively, Handler mode can be configured to use the process stack ( R1 3

banked register).

Out of reset the Cortex processor will run in a ‘flat’ configuration. Both Thread and Handler modes execute in

privileged mode, so there are no restrictions on access to any processor resources. Both the Thread and Handler

modes use the main stack. In order to start execution, the Cortex processor simply needs the reset vector and the

start address of the stack to be configured before you can start to execute your application C code. However, if

you are using an RTOS or are developing a safety-critical application, the chip can be used in a mode advanced

configuration where Handler mode (exceptions and the RTOS) runs in privileged mode and uses the main stack

while application code runs in Thread mode with unprivileged access and uses the process stack. This way the

system code and the application code are partitioned and errors in the application code will not cause the RTOS

to crash.

2.3.4 Thumb-2 Instruction Set

The ARM7 and ARM9 CPUs can execute two instruction sets: the ARM 32-bit instruction set and the Thumb 16-

bit instruction set. This allows a developer to optimise his program by selecting the instruction set used for

The Cortex-M3 can be used in a ‘flat’ simple mode. It

is also designed to support real-time operating

systems. It has Handler and Thread modes that can

be configured to use the main and process stacks

and have privileged access to the Cortex system

control registers.

Chapter 2: Cortex Overview

2.3.5 M e m o r y Map

The Cortex-M3 processor is a standardised microcontroller core and as such has a well-defined memory map.

Despite the multiple internal busses this memory map is a linear 4 Gbyte address space.

The first 1Gbyte of memory is split evenly between a code region and a SRAM region. The code space is

optimised to be executed from the I-Code bus. Similarly, the SRAM is reached with the D-code bus. Although

code can be loaded and executed from the SRAM, the instructions would be fetched using the system bus, wh i c h

incurs an extra wait state. It is likely that code would run slower from SRAM than from on-chip FLASH memory

located in the code region. The next 0.5 Gbyte of memory is the on-chip peripheral region. All user peripherals

provided by the microcontroller vendor will be located in this region. The first 1 Mbyte of both the SRAM and

Peripheral regions is bit-addressable using a technique called bit banding. Since all the SRAM and all the user

peripherals on the STM32 are located in these regions all the memory locations of the STM32 can be

manipulated in a word-wide or bitwise fashion. The next 2 Gbyte address space is allocated to external memory-

mapped SRAM and peripherals. The final 0.5 Gbyte is allocated to the internal Cortex processor peripherals and

a region for future vendor specific enhancements to the Cortex processor. All of the Cortex processor registers

are at fixed locations for all Cortex-based microcontrollers. This allows code to be more easily ported between

different STM32 variants and indeed other vendors’ Cortex-based microcontrollers. One processor to learn, one

set of tools to invest in and large amounts of reusable code across a wide range of microcontrollers.

The Cortex-M3 defines a fixed 4

Gb memory map that specifies

regions for code SRAM

peripherals, external memory

and devices and the Cortex

system registers. This memory

map is common to all Cortex-

based devices.

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