QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual, Rev. 0
xx Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
Chapter 8
Frame Manager (FMan)
8.1 FMan Overview ............................................................................................................... 8-1
8.1.1 FMan Terms, Acronyms, and Abbreviations............................................................... 8-1
8.1.2 FMan Features Summary............................................................................................. 8-3
8.2 FMan High-Level Functional Description....................................................................... 8-5
8.2.1 FMan Hardware Ports.................................................................................................. 8-5
8.2.2 FMan Network Interfaces............................................................................................ 8-5
8.2.2.1 FMan Parse Function............................................................................................... 8-6
8.2.2.2 FMan Classification, Distribution, and Policing ..................................................... 8-6
8.2.2.2.1 FMan Policer Function Features and Considerations.......................................... 8-7
8.2.3 FMan-to-SoC Interfaces .............................................................................................. 8-8
8.2.4 FMan Module Architecture ......................................................................................... 8-8
8.2.5 FMan User-Configurable Pipeline Architecture—Introducing the NIA................... 8-11
8.2.5.1 Packet Flow in the FMan Configurable Pipeline Architecture.............................. 8-11
8.2.5.2 Role of the NIA in the FMan Configurable Pipeline Architecture........................ 8-11
8.2.6 FMan Multitasking—Introducing the Task and TNUM............................................ 8-12
8.2.7 FMan Timestamp....................................................................................................... 8-12
8.2.8 FMan Memory Map—High-Level Concept.............................................................. 8-12
8.2.9 FMan Internal Memory.............................................................................................. 8-12
8.2.9.1 FMan Internal Memory for Tx, Rx, and O/H FIFOs............................................. 8-13
8.2.9.2 FMan Internal Memory for FMan Controller Coarse Classification..................... 8-13
8.2.10 FMan Functional Flows............................................................................................. 8-13
8.2.10.1 Receive (Rx) Flows ............................................................................................... 8-13
8.2.10.1.1 Configurable Receive (Rx) Flows ..................................................................... 8-13
8.2.10.1.2 Receive (Rx) Flow Example with Coarse Classification .................................. 8-16
8.2.10.2 Transmit (Tx) Flow Example ................................................................................ 8-20
8.2.10.3 FMan Offline Port Flow Example ......................................................................... 8-22
8.2.10.4 Independent Mode (IM) Flow ............................................................................... 8-23
8.2.10.5 Host Command Flow............................................................................................. 8-24
8.3 FMan Detailed Functional Description.......................................................................... 8-26
8.3.1 FMan Hardware Ports................................................................................................ 8-26
8.3.1.1 FMan PortIDs ........................................................................................................ 8-27
8.3.2 FMan Detailed Memory Map .................................................................................... 8-27
8.3.2.1 Hardware Port Pages in the FMan Memory Map.................................................. 8-29
8.3.2.2 Examples for the Evaluation of Addresses of FMan Registers............................. 8-30
8.3.2.2.1 Calculate the SoC Abolute Address for an FMan Register............................... 8-30
8.3.2.2.2 Calculate the SoC Abolute Address for FMan Hardware Port Page Register... 8-30
8.3.3 FMan Frame Internal Context (IC)............................................................................ 8-31
8.3.3.1 Override IC from FQD or Data Buffer.................................................................. 8-32