Cortex-M处理器家族开发者指南：基于MDK-ARM的实战教程

Cortem-M

Processors

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"Newnes-The Designer's Guide to the Cortex-M Processor Family-2013" 是一本关于Cortex-M处理器家族的设计者指南，作者Trevor Martin采用教程方式深入浅出地介绍了这一处理器架构和CMSIS（Cortex Microcontroller Software Interface Standard）软件编程标准。本书的目标读者是希望了解和开发Cortex-M处理器应用软件的工程师和学习者。它不仅对Cortex-M处理器进行了详细介绍，还提供了开发技巧和实践指导。书中包含一系列示例，通过最小化的代码量来展示每个章节的关键原理。这些示例都是为了配合MDK-ARM的评估版进行编译而设计的，便于读者动手实践。 Cortex-M处理器家族是ARM公司推出的一种微控制器核心系列，广泛应用于嵌入式系统和物联网设备。它们以其高效能、低功耗和易于编程的特性受到欢迎。CMSIS则是为Cortex-M处理器设计的一套标准化软件接口，旨在简化硬件抽象层，提高软件的可移植性和兼容性。本书的结构可能包括以下几个部分： 1. **处理器架构介绍**：详细阐述Cortex-M处理器的体系结构，如冯诺依曼或哈佛架构、寄存器布局、中断处理机制、存储器管理单元（MMU）以及调试支持等。 2. **指令集架构（ISA）**：解释Cortex-M处理器所使用的指令集，包括数据处理、分支、加载/存储以及浮点运算指令等。 3. **CMSIS详解**：详细解析CMSIS库的功能和使用方法，如中断向量表、设备驱动模型、RTOS（实时操作系统）接口等。 4. **开发环境与工具链**：介绍如何配置和使用MDK-ARM等开发工具，包括编译器、调试器和模拟器的使用。 5. **程序设计与优化**：提供编写高效C或C++代码的技巧，如内存管理、中断服务程序设计、能耗优化等。 6. **硬件接口与外设**：讲解如何与Cortex-M处理器连接的各种外设进行通信，如GPIO、定时器、串行接口、ADC和DMA等。 7. **实例分析与项目实践**：通过具体项目案例，展示如何将理论知识应用于实际设计中，增强读者的实践能力。 8. **调试与测试**：介绍常用的调试技巧和工具，如何进行性能测试和错误排查。 9. **安全与可靠性**：讨论Cortex-M处理器在安全和可靠性方面的考虑，如固件更新、错误检测和保护机制。通过本书，读者不仅可以理解Cortex-M处理器的工作原理，还能掌握开发高效的嵌入式软件所需的技能，为未来硬件和软件的标准化打下坚实基础。

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architecture increases the performance of the Cortex-M processor but does not introduce

any additional complexity for the programmer.

ARM

Thumb

Thumb-2

Instruction flow

32-bit

32-bit 32-bit 32-bit

16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit

16-bit 16-bit 16-bit

16-bit

32-bit 32-bit 32-bit 32-bit

ARM

decoder

Thumb

decoder

ARM core

Figure 1.7

Earlier ARM CPUs had two instruction sets, ARM (32 bit) and Thumb (16 bit). The Cortex-M

processors have an instruction set called Thumb-2 which is a blend of 16- and 32-bit instructions.

The earli er ARM CPUs, ARM7 and ARM9, s upported two instr uction sets. This code could

be c ompiled either as 32-bit ARM code or as 16-bit Thumb code. The ARM instruc tion set

would allow code to be written for maximum performance, while Thumb code would

achieve a greater code density. During development, the programmer had to decide which

function should be compi led with the ARM 32-bit instruction set and whi ch should be bu ilt

using the Thumb 16-bit instructio n set. The linker would then interwork the two instruction

sets together. While the Cortex-M processors are code compatible with the original Thumb

instruction set, they are designe d to execute an extended version of the Thumb ins truction

set called T humb-2. Thumb-2 is a blend of 16- and 32-bit instructions that has been

designed to be very C friendly and eff icient. For even the smallest Cortex-M project, all of

the code can be written in a high-level language, typically C, without a ny need to us e an

assembler.

Relative DMIPS/MHz

1.4

1.2

0.8

0.6

0.4

0.2

ARM7

(Thumb)

ARM7

(ARM)

Cortex-M3

and M4

Figure 1.8

The Corte x-M3 and Cortex-M4 Thumb-2 instruction set achieves higher performance levels than

either the Thumb or the ARM instruction set running on the ARM7.

Introduction to the Cortex-M Processor Family 7

end of the Cortex-M family, it still packs a lot of processing power. The Cortex-M0

processor has the same NVIC as the Cortex-M3, but it is limited to a maximum of 32

interrupt lines from the microcontroller peripherals. The NVIC also contains the systick

timer that is fully compatible with the Cortex-M3. Most RTOS that run on the Cortex-M3

and Cortex-M4 will also run on the Cortex-M0, though the vendor will need to do a

dedicated port and recompile the RTOS code. As a developer, the biggest difference you

will find between using the Cortex-M0 and the Cortex-M3 is its debug capabilities. While on

the Cortex-M3 and Cortex-M4 there is extensive real-time debug support, the Cortex-M0 has

a more modest debug architecture. On the Cortex-M0, the DWT unit does not support data

trace and the ITM is not fitted, so we are left with basic run control (i.e., run, halt, single

stepping and breakpoints, and watchpoints) and on-the-fly memory/peripheral accesses. This

is still an enhancement from the JTAG support provided on ARM7 and ARM9 CPUs.

ARM Cortex-M0 8-bit or 16-bit

Energy

efficient

Energy

cost

Power

TimeTime

Figure 1.12

The Corte x-M0 is design ed to suppor t low-power standby modes. Compared to an 8- or 16-bit

MCU, it can stay in sleep mode for much more time because it needs to execute fewer instructions

than an 8/16-bit device to achieve the same result.

While the Cortex-M0 is designed to be a high pe rformance microcontrolle r process or it

has a relat ively l ow ga te c ount. Thi s make s it ideal for both lo w cost and low power

devices. The typical power consumption of the Cortex-M0 is 16 µW/MHz whe n runn ing

and almost zero when in its low-power sleep mode. While other 8- and 16-bit

architectures can a lso achieve s imilar low-power figures, they need to e xecute far more

instructions than the Cortex-M0 to achieve the same end res ult. This means extra cycles

and extra c ycles would mean more power consumpt ion. If we pick a goo d exa mple f or

Cortex-M0 such as a 16 3 16 multiply, then the Cortex-M0 can perform this calculation in

one cycle. In comparison, an 8-bit typical architecture like the 8051 will need at least 48

cycles and a 16-bit a rchitecture will need 8 cycles. This is not only a performance

advantage but also an ene rgy ef ficiency advantage as well.

10 Chapter 1

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Cortex-M处理器家族开发者指南：基于MDK-ARM的实战教程

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