ARM®与Thumb®-2指令集速查卡片

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"ARM® and Thumb®-2 Instruction Set Quick Reference Card" ARM 和 Thumb-2 指令集是 ARM 架构中两种重要的指令集，它们用于构建和控制 ARM 处理器的操作。Thumb-2 是 Thumb 指令集的增强版，提供更高的代码密度和性能，适用于资源有限的嵌入式系统以及需要高效能计算的移动设备。 1. **ARM 指令集**：ARM 指令集通常为 32 位，并且在设计时注重效率和性能。它包含一系列数据处理、分支、加载和存储指令，用于执行各种计算任务。ARM 指令通常包括操作码、操作数和可能的立即数或寄存器引用。 2. **Thumb-2 指令集**：Thumb-2 旨在提供与 ARM 指令集相当的功能，但使用更小的 16 位格式。这使得代码占用更少的空间，对于资源受限的环境非常有用。Thumb-2 扩展了原始 16 位 Thumb 指令集，引入了 32 位指令，以实现更复杂的操作和更高的性能。 3. **指令格式**：指令格式在描述中提到的表格中有所说明，例如 `<Rm{,<opsh>}` 表示一个寄存器 Rm，可以加上一个可选的位移操作（opsh），这可能是立即数或寄存器的位移。`<Operand2>` 则指出了灵活的第二个操作数，可能包括位移和旋转操作。 4. **寄存器操作**：在 ARM 和 Thumb-2 指令集中，寄存器是数据处理的主要载体。`<reglist>` 指定一组用逗号分隔的寄存器，而 `<reglist-PC>` 和 `<reglist+PC>` 包含 PC（程序计数器）寄存器，但前者不包括，后者则包括。 5. **处理器状态寄存器（PSR）**：PSR 包括 CPSR（当前处理器状态寄存器）和 SPSR（保存的处理器状态寄存器）。这些寄存器保存了处理器的条件标志和其他关键状态信息。 6. **标志和中断**：C* 和 V* 标志表示条件标志，其行为在 ARM 架构的不同版本中可能有所不同。`<iflags>` 用于指定中断标志，如 abort、interrupt 和 fastinterrupt。 7. **半寄存器操作**：x 和 y 分别表示半寄存器 [15:0] 和 [31:16]，在某些指令中用于访问 32 位寄存器的上半部分或下半部分。 8. **位移和旋转**：`<Rs|sh>` 允许 Rs 或立即值作为位移量，根据表中的说明，位移类型和允许的值各不相同。 9. **立即数**：`<imm8m>` 描述了一个由右旋转的 8 位值形成的 32 位常量，旋转的位数是偶数。 10. **处理器模式**：`<p_mode>` 提及了处理器模式，如用户模式、系统模式、中断模式等，不同的模式下，处理器对指令和资源的访问权限不同。这些是 ARM 和 Thumb-2 指令集的一些核心概念。在实际编程或调试过程中，理解这些指令和它们的格式对于有效地利用 ARM 处理器的潜力至关重要。参考卡片提供了快速查阅这些关键要素的便捷方式。

ARM

and Thumb

-2 Instruction Set

Quick Reference Card

Key to Tables

Rm {, <opsh>} See Table Register, optionally shifted by constant

<Operand2> See Table Flexible Operand 2. Shift and rotate are only available as part of Operand2. <reglist> A comma-separated list of registers, enclosed in braces { and }.

<fields> See Table PSR fields. <reglist-PC> As <reglist>, must not include the PC.

<PSR> Either CPSR (Current Processor Status Register) or SPSR (Saved Processor Status Register) <reglist+PC> As <reglist>, including the PC.

C*, V* Flag is unpredictable in Architecture v4 and earlier, unchanged in Architecture v5 and later. +/- + or –. (+ may be omitted.)

<Rs|sh> Can be Rs or an immediate shift value. The values allowed for each shift type are the same as those § See Table ARM architecture versions.

shown in Table Register, optionally shifted by constant. <iflags> Interrupt flags. One or more of a, i, f (abort, interrupt, fast interrupt).

x,y B meaning half-register [15:0], or T meaning [31:16]. <p_mode> See Table Processor Modes

<imm8m> ARM: a 32-bit constant, formed by right-rotating an 8-bit value by an even number of bits. SPm SP for the processor mode specified by <p_mode>

Thumb: a 32-bit constant, formed by left-shifting an 8-bit value by any number of bits, or a bit <lsb> Least significant bit of bitfield.

pattern of one of the forms 0xXYXYXYXY, 0x00XY00XY or 0xXY00XY00. <width> Width of bitfield. <width> + <lsb> must be <= 32.

<prefix> See Table Prefixes for Parallel instructions {X} RsX is Rs rotated 16 bits if X present. Otherwise, RsX is Rs.

{IA|IB|DA|DB} Increment After, Increment Before, Decrement After, or Decrement Before. {!} Updates base register after data transfer if ! present (pre-indexed).

IB and DA are not available in Thumb state. If omitted, defaults to IA. {S} Updates condition flags if S present.

<size> B, SB, H, or SH, meaning Byte, Signed Byte, Halfword, and Signed Halfword respectively. {T}

User mode privilege if T present.

SB and SH are not available in STR instructions. {R} Rounds result to nearest if R present, otherwise truncates result.

Operation § Assembler S updates Action Notes

Add Add ADD{S} Rd, Rn, <Operand2> N Z C V Rd := Rn + Operand2 N

with carry ADC{S} Rd, Rn, <Operand2> N Z C V Rd := Rn + Operand2 + Carry N

wide T2 ADD Rd, Rn, #<imm12> Rd := Rn + imm12, imm12 range 0-4095 T, P

saturating {doubled} 5E Q{D}ADD Rd, Rm, Rn Rd := SAT(Rm + Rn) doubled: Rd := SAT(Rm + SAT(Rn * 2)) Q

Address Form PC-relative address ADR Rd, <label> Rd := <label>, for <label> range from current instruction see Note L N, L

Subtract Subtract SUB{S} Rd, Rn, <Operand2> N Z C V Rd := Rn – Operand2 N

with carry SBC{S} Rd, Rn, <Operand2> N Z C V Rd := Rn – Operand2 – NOT(Carry) N

wide T2 SUB Rd, Rn, #<imm12> N Z C V Rd := Rn – imm12, imm12 range 0-4095 T, P

reverse subtract RSB{S} Rd, Rn, <Operand2> N Z C V Rd := Operand2 – Rn N

reverse subtract with carry RSC{S} Rd, Rn, <Operand2> N Z C V Rd := Operand2 – Rn – NOT(Carry) A

saturating {doubled} 5E Q{D}SUB Rd, Rm, Rn Rd := SAT(Rm – Rn) doubled: Rd := SAT(Rm – SAT(Rn * 2)) Q

Exception return without stack SUBS PC, LR, #<imm8> PC = LR – imm8, CPSR = SPSR(current mode), imm8 range 0-255. T

Parallel

arithmetic

Halfword-wise addition 6 <prefix>ADD16 Rd, Rn, Rm Rd[31:16] := Rn[31:16] + Rm[31:16], Rd[15:0] := Rn[15:0] + Rm[15:0] G

Halfword-wise subtraction 6 <prefix>SUB16 Rd, Rn, Rm Rd[31:16] := Rn[31:16] – Rm[31:16], Rd[15:0] := Rn[15:0] – Rm[15:0] G

Byte-wise addition 6 <prefix>ADD8 Rd, Rn, Rm Rd[31:24] := Rn[31:24] + Rm[31:24], Rd[23:16] := Rn[23:16] + Rm[23:16],

Rd[15:8] := Rn[15:8] + Rm[15:8], Rd[7:0] := Rn[7:0] + Rm[7:0]

Byte-wise subtraction 6 <prefix>SUB8 Rd, Rn, Rm Rd[31:24] := Rn[31:24] – Rm[31:24], Rd[23:16] := Rn[23:16] – Rm[23:16],

Rd[15:8] := Rn[15:8] – Rm[15:8], Rd[7:0] := Rn[7:0] – Rm[7:0]

Halfword-wise exchange, add, subtract 6 <prefix>ASX Rd, Rn, Rm Rd[31:16] := Rn[31:16] + Rm[15:0], Rd[15:0] := Rn[15:0] – Rm[31:16] G

Halfword-wise exchange, subtract, add 6 <prefix>SAX Rd, Rn, Rm Rd[31:16] := Rn[31:16] – Rm[15:0], Rd[15:0] := Rn[15:0] + Rm[31:16] G

Unsigned sum of absolute differences 6 USAD8 Rd, Rm, Rs Rd := Abs(Rm[31:24] – Rs[31:24]) + Abs(Rm[23:16] – Rs[23:16])

+ Abs(Rm[15:8] – Rs[15:8]) + Abs(Rm[7:0] – Rs[7:0])

and accumulate 6 USADA8 Rd, Rm, Rs, Rn Rd := Rn + Abs(Rm[31:24] – Rs[31:24]) + Abs(Rm[23:16] – Rs[23:16])

+ Abs(Rm[15:8] – Rs[15:8]) + Abs(Rm[7:0] – Rs[7:0])

Saturate Signed saturate word, right shift 6 SSAT Rd, #<sat>, Rm{, ASR <sh>} Rd := SignedSat((Rm ASR sh), sat). <sat> range 1-32, <sh> range 1-31. Q, R

Signed saturate word, left shift 6 SSAT Rd, #<sat>, Rm{, LSL <sh>} Rd := SignedSat((Rm LSL sh), sat). <sat> range 1-32, <sh>

range 0-31. Q

Signed saturate two halfwords 6 SSAT16 Rd, #<sat>, Rm Rd[31:16] := SignedSat(Rm[31:16], sat),

Rd[15:0] := SignedSat(Rm[15:0], sat). <sat> range 1-16.

Unsigned saturate word, right shift 6 USAT Rd, #<sat>, Rm{, ASR <sh>} Rd := UnsignedSat((Rm ASR sh), sat). <sat> range 0-31, <sh> range 1-31. Q, R

Unsigned saturate word, left shift 6 USAT Rd, #<sat>, Rm{, LSL <sh>} Rd := UnsignedSat((Rm LSL sh), sat). <sat> range 0-31, <sh> range 0-31. Q

Unsigned saturate two halfwords 6 USAT16 Rd, #<sat>, Rm Rd[31:16] := UnsignedSat(Rm[31:16], sat),

Rd[15:0] := UnsignedSat(Rm[15:0], sat). <sat> range 0-15.

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