7系列FPGA与MIG生成DDR2 IP核详解

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"这篇文档是关于Xilinx 7系列FPGA使用Memory Interface Solutions (MIG)生成DDR2 IP核的用户指南，版本1.7，发布于2012年10月16日。该指南详细介绍了如何配置和使用DDR2内存接口，以及相关的IP功能。" 在Xilinx 7系列FPGA中，Memory Interface Solutions (MIG) 是一种强大的工具，用于简化高速存储器接口如DDR2的设计过程。DDR2（Double Data Rate Second Generation Synchronous Dynamic Random-Access Memory）是一种广泛应用的内存技术，它提供比第一代DDR更高的数据传输速率，同时降低了功耗。 MIG IP核是Xilinx提供的预配置硬件模块，能够帮助设计者快速、准确地集成DDR2内存到FPGA设计中。以下是一些关键知识点： 1. **DDR2内存结构**：DDR2内存工作在同步模式下，数据在时钟的上升沿和下降沿同时传输，从而实现双倍数据速率。它具有多个Bank，可以并行处理多个读写请求，提高系统性能。 2. **MIG流程**：使用MIG时，设计者首先需要配置IP核，指定内存类型（DDR2）、速度等级、总线宽度等参数。然后，MIG会生成必要的逻辑、时序控制器和PHY层，以确保与DDR2内存芯片的正确通信。 3. **IP配置**：在Xilinx ISE或Vivado设计环境中，设计者通过MIG GUI进行配置，包括选择内存芯片型号、设置时序参数、定义接口宽度等。这些设置会影响到整个系统的性能和兼容性。 4. **接口设计**：MIG生成的IP核提供了与FPGA内部逻辑交互的AXI4-Stream接口，允许高效的数据传输。设计者需要根据应用需求，适配这个接口到他们的系统设计中。 5. **时序约束**：为了确保设计满足内存的时序要求，MIG会自动生成必要的时序约束，这些约束在综合和实现阶段必须被正确应用。 6. **物理层(PHY)**：MIG还包括一个经过优化的PHY层，处理与DDR2内存芯片的物理接口，包括信号调理、时钟恢复和数据对齐等功能。 7. **调试和验证**：MIG提供了一套全面的测试平台和波形视图，便于设计者在硬件上进行功能验证和性能调试。 8. **性能优化**：MIG支持多种优化选项，如预读取、写后读等，以提高内存带宽和降低访问延迟。 9. **合规性和标准**：Xilinx MIG符合JEDEC DDR2标准，确保了设计的兼容性和可靠性。 Xilinx 7Series_MIS提供了详细的步骤和工具，使得开发者能够在7系列FPGA中有效地集成DDR2内存，实现了高性能、低延迟的系统设计。然而，重要的是要注意，虽然MIG大大简化了设计过程，但设计者仍需理解内存接口的基本原理和相关时序要求，以确保设计的成功。同时，Xilinx声明其提供的材料“AS IS”，不承担任何明示或暗示的保修责任。在实际使用中，设计者应遵循文档中的指导，并充分测试以避免潜在的问题。

16 www.xilinx.com 7 Series FPGAs Memory Interface Solutions

UG586 October 16, 2012

Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution

MIG Output Options

1. Select the Create Design radio button to create a new memory controller design. Enter

a component name in the Component Name field (Figure 1-8).

2. Choose the number of controllers to be generated. This option determines the

replication of further pages.

3. DDR2 and DDR3 SDRAM designs support the memory-mapped AXI4 interface. The

AXI4 interface is implemented in Verilog only. If an AXI4 interface is required, select

the language as “Verilog” in the CORE Generator tool before invoking the MIG tool. If

the AXI4 interface is not selected, the user interface (UI) is the primary interface. The

axi_7series_ddrx IP from the EDK flow only supports DDR3 SDRAMs and has the AXI

support always turned on.

MIG outputs are generated with the folder name <component name>.

Note:

Only alphanumeric characters can be used for <component name>. Special characters

cannot be used. This name should always start with an alphabetical character and can end with

an alphanumeric character.

When invoked from XPS, the component name is corrected to be the IP instance name

from XPS.

4. Click Next to display the Pin Compatible FPGAs page.

X-Ref Target - Figure 1-8

Figure 1-8: MIG Output Options

UG586_c1_09_120311

20 www.xilinx.com 7 Series FPGAs Memory Interface Solutions

UG586 October 16, 2012

Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution

If the design has multiple controllers, the controller options page is repeated for each of the

controllers. This page is partitioned into a maximum of nine sections. The number of

partitions depends on the type of memory selected. The controller options page also

contains these pull-down menus to modify different features of the design:

• Frequency – This feature indicates the operating frequency for all the controllers. The

frequency block is limited by factors such as the selected FPGA and device speed

grade. In the EDK flow, an extra check box (selected by default) allows the user to

specify that the frequency information should be calculated automatically from EDK.

• Input Clock Period – The desired input clock period is selected from the list. These

values are determined by the memory clock period chosen and the allowable limits of

the parameters. See Design Guidelines, page 144 for more information on the PLL

parameter limits.

• PHY to Controller Clock Ratio – This feature determines the ratio of the physical

layer (memory) clock frequency to the controller and user interface clock frequency.

The 2:1 ratio lowers the maximum memory interface frequency due to fabric timing

limitations. The user interface data bus width of the 2:1 ratio is 4 times the width of

the physical memory interface width, while the bus width of the 4:1 ratio is 8 times the

physical memory interface width. The 2:1 ratio has lower latency. The 4:1 ratio is

necessary for the highest data rates.

• Vccaux_io – Vccaux_io is set based on the period/frequency setting. 2.0V is required

at the highest frequency settings in the High Performance column. The MIG tool

automatically selects 2.0V when required. Either 1.8 or 2.0V can be used at lower

frequencies. Groups of banks share the Vccaux_io supply. See the 7 Series FPGAs

SelectIO Resources User Guide [Ref 1] and the 7 Series FPGAs Packaging and Pinout

Specification [Ref 2] for more information.

• Memory Type – This feature selects the type of memory parts used in the design.

• Memory Part – This option selects a memory part for the design. Selections can be

made from the list or a new part can be created.

• Data Width – The data width value can be selected here based on the memory type

selected earlier. The list shows all supported data widths for the selected part. One of

the data widths can be selected. These values are generally multiples of the individual

device data widths. In some cases, the width might not be an exact multiple. For

example, 16 bits is the default data width for x16 components, but 8 bits is also a valid

value.

• Data Mask – This option allocates data mask pins when selected. This option should

be deselected to deallocate data mask pins and increase pin efficiency. This option is

disabled for memory parts that do not support data mask.

• Ordering – This feature allows the memory controller to reorder commands to

improve the memory bus efficiency.

• Memory Details – The bottom of the Controller Options page (Figure 1-11, page 19)

displays the details for the selected memory configuration (Figure 1-12).

1. Select the appropriate frequency. Either use the spin box or enter a valid value using

the keyboard. Values entered are restricted based on the minimum and maximum

frequencies supported.

X-Ref Target - Figure 1-12

Figure 1-12: Memory Details

UG586_c1_20_091410

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