Intel 82C54: CHMOS Programmable Interval Timer详解

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"82C54 CHMOS可编程间隔定时器是英特尔公司的一款高性能计数定时器，兼容所有英特尔和其他大多数微处理器。它在8MHz的8086/88和80186/188系统中实现零等待状态操作，能够处理直流到10MHz的输入（对于82C54-2）。该器件有三个独立的16位计数器，采用低功耗CHMOS技术，电流消耗仅为10mA@8MHz计数频率。82C54完全兼容TTL标准，具有六种可编程计数模式，支持二进制或BCD计数，并且提供状态读回命令。该定时器可应用于事件计数器、已逝时间指示器、可编程单次触发器等多种应用场景。此外，82C54与HMOS 8254引脚兼容，功能上扩展了8253。" 82C54 CHMOS可编程间隔定时器是微计算机系统设计中的重要组件，主要用于解决各种定时控制问题。这款设备采用了高速的"零等待状态"操作，意味着在特定系统配置下，它能在不影响处理器性能的情况下工作，这对于需要精确时间控制的系统尤其重要。该定时器包含三个独立的16位计数器，每个计数器都能处理高达10MHz的时钟输入。这种高频率处理能力使得82C54在需要快速响应的实时应用中表现出色。不仅如此，所有计数模式都可通过软件编程设置，提供了极大的灵活性。 82C54提供了六种可编程计数器模式，包括计数模式、门控模式、方波发生器模式、捕捉模式、重装载模式以及看门狗定时器模式。这些模式使得82C54能适应多种复杂的应用场景，如精确的时间间隔测量、周期性任务触发、系统故障检测等。低功耗CHMOS设计使得82C54在保持高性能的同时，还能有效降低功耗，适合电池供电或对电源敏感的设备使用。其完全兼容TTL逻辑标准，意味着它可以轻松地集成到现有的数字电路中。24针DIP和28针PLCC封装选项进一步增强了其在不同硬件平台上的适应性。 82C54的一个独特特性是状态读回命令，允许用户在运行过程中检查定时器的状态，这对于调试和系统监控非常有用。由于其与HMOS 8254引脚兼容并扩展了8253的功能，82C54成为了升级旧系统或设计新系统时的理想选择。 82C54 CHMOS可编程间隔定时器是一款功能强大、灵活多用的定时解决方案，广泛应用于工业控制、数据通信、仪器仪表以及计算机系统等领域。它的高性能、低功耗和丰富的功能集使其成为微计算机系统设计不可或缺的一部分。

82C54

231244–6

Figure 5. Internal Block Diagram of a Counter

The status register, shown in the Figure, when

latched, contains the current contents of the Control

Word Register and status of the output and null

count flag. (See detailed explanation of the Read-

Back command.)

The actual counter is labelled CE (for ‘‘Counting Ele-

ment’’). It is a 16-bit presettable synchronous down

counter.

and OL

are two 8-bit latches. OL stands for

‘‘Output Latch’’; the subscripts M and L stand for

‘‘Most significant byte’’ and ‘‘Least significant byte’’

respectively. Both are normally referred to as one

unit and called just OL. These latches normally ‘‘fol-

low’’ the CE, but if a suitable Counter Latch Com-

mand is sent to the 82C54, the latches ‘‘latch’’ the

present count until read by the CPU and then return

to ‘‘following’’ the CE. One latch at a time is enabled

by the counter’s Control Logic to drive the internal

bus. This is how the 16-bit Counter communicates

over the 8-bit internal bus. Note that the CE itself

cannot be read; whenever you read the count, it is

the OL that is being read.

Similarly, there are two 8-bit registers called CR

and CR

(for ‘‘Count Register’’). Both are normally

referred to as one unit and called just CR. When a

new count is written to the Counter, the count is

stored in the CR and later transferred to the CE. The

Control Logic allows one register at a time to be

loaded from the internal bus. Both bytes are trans-

ferred to the CE simultaneously. CR

and CR

are

cleared when the Counter is programmed. In this

way, if the Counter has been programmed for one

byte counts (either most significant byte only or least

significant byte only) the other byte will be zero.

Note that the CE cannot be written into; whenever a

count is written, it is written into the CR.

The Control Logic is also shown in the diagram. CLK

n, GATE n, and OUT n are all connected to the out-

side world through the Control Logic.

82C54 SYSTEM INTERFACE

The 82C54 is treated by the systems software as an

array of peripheral I/O ports; three are counters and

the fourth is a control register for MODE program-

ming.

Basically, the select inputs A

connect to the A

address bus signals of the CPU. The CS can be

derived directly from the address bus using a linear

select method. Or it can be connected to the output

of a decoder, such as an Intel 8205 for larger sys-

tems.

231244–7

Figure 6. 82C54 System Interface

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