Exynos4412微处理器用户手册详解

需积分: 12 22 浏览量更新于2024-07-20 收藏 24MB PDF 举报

Exynos4412用户手册详解 Exynos4412是 Samsung Electronics Co., Ltd. 发布的一款高性能的微处理器，基于ARM Cortex-A9架构设计。该处理器主要应用于智能手机、平板电脑等移动设备中，提供了强大的计算能力和低功耗特性。根据手册，Exynos4412的存储器架构可以分为多个部分： 1. iROM：存储器地址从0x0000_0000到0x0001_0000，大小为64 KB，是一块镜像存储器，用于存储bootloader和其他固件程序。 2. iRAM：存储器地址从0x0202_0000到0x0206_0000，大小为256 KB，用于存储操作系统和应用程序。 3. Data memory or general purpose of Samsung Reconfigurable Processor SRP：存储器地址从0x0300_0000到0x0302_0000，大小为128 KB，用于存储数据和配置信息。 4. I-cache or general purpose of SRP：存储器地址从0x0302_0000到0x0303_0000，大小为64 KB，用于存储指令缓存和配置信息。 5. Configuration memory (write only) of SRP：存储器地址从0x0303_0000到0x0303_9000，大小为36 KB，用于存储SRP的配置信息。 6. AudioSS's SFR region：存储器地址从0x0381_0000到0x0383_0000，用于存储音频处理器的配置信息。 7. Static Read Only Memory Controller (SMC)：存储器地址从0x0400_0000到0x0500_0000，大小为16 MB，用于存储操作系统和应用程序。 8. Dynamic Memory Controller (DMC)：存储器地址从0x4000_0000到0xA000_0000，大小为1.5 GB，用于存储操作系统和应用程序。 Exynos4412还提供了多种接口，包括UART、SPI、I2C、USB、SD/MMC、HDMI等，满足了移动设备的多种需求。在使用Exynos4412时，需要注意一些重要的注意事项： * Samsung Electronics Co., Ltd. 保留了对该手册的修改权利，用户需要遵守相关的使用条款。 * 该手册仅供参考，不提供任何arranty、representation或guarantee。 * 用户需要自行承担使用Exynos4412的风险和责任。 Exynos4412用户手册提供了该处理器的详细信息，包括存储器架构、接口和使用注意事项，为开发者和用户提供了有价值的参考资料。

35.8 IO Description .................................................................................................................................... 35-19

35.9 Register Description ........................................................................................................................... 35-20

35.9.1 Register Map Summary .............................................................................................................. 35-20

36 IIS-BUS INTERFACE ................................................................................. 36-1

36.1 Overview .............................................................................................................................................. 36-1

36.2 Features ............................................................................................................................................... 36-1

36.3 Block Diagram ...................................................................................................................................... 36-2

36.4 Functional Description ......................................................................................................................... 36-3

36.4.1 Master/Slave Mode ....................................................................................................................... 36-3

36.4.2 DMA Transfer ............................................................................................................................... 36-4

36.4.3 Audio Serial Data Format ............................................................................................................. 36-5

36.4.4 PCM Word Length and BFS Divider ............................................................................................. 36-8

36.4.5 BFS Divider and RFS Divider ....................................................................................................... 36-8

36.4.6 RFS Divider and Root Clock ......................................................................................................... 36-8

36.5 Programming Guide ............................................................................................................................. 36-9

36.5.1 Initialization ................................................................................................................................... 36-9

36.5.2 Play Mode (Tx Mode) with DMA ................................................................................................... 36-9

36.5.3 Recording Mode (Rx Mode) with DMA ......................................................................................... 36-9

36.5.4 Example Code ............................................................................................................................ 36-10

36.6 I/O Description ................................................................................................................................... 36-16

36.7 Register Description ........................................................................................................................... 36-17

36.7.1 Register Map Summary .............................................................................................................. 36-17

37 AC97 CONTROLLER ................................................................................ 37-1

37.1 Overview .............................................................................................................................................. 37-1

37.2 Features ............................................................................................................................................... 37-1

37.3 AC97 Controller Operation ................................................................................................................... 37-2

37.3.1 Block Diagram .............................................................................................................................. 37-2

37.3.2 Internal Data Path ......................................................................................................................... 37-3

37.3.3 Operation Flow Chart ................................................................................................................... 37-4

37.3.4 AC-link Digital Interface Protocol .................................................................................................. 37-5

37.3.5 AC-link Input Frame (SDATA_IN) ................................................................................................. 37-7

37.3.6 AC97 Power-Down ....................................................................................................................... 37-9

37.4 I/O Description ................................................................................................................................... 37-12

37.5 Register Description ........................................................................................................................... 37-13

37.5.1 Register Map Summary .............................................................................................................. 37-13

38 PCM AUDIO INTERFACE ......................................................................... 38-1

38.1 Overview .............................................................................................................................................. 38-1

38.2 Features ............................................................................................................................................... 38-1

38.3 PCM Audio Interface ............................................................................................................................ 38-2

38.4 PCM Timing ......................................................................................................................................... 38-3

38.5 I/O Description ..................................................................................................................................... 38-5

38.6 Register Description ............................................................................................................................. 38-6

38.6.1 Register Map Summary ................................................................................................................ 38-6

39 SPDIF TRANSMITTER .............................................................................. 39-1

39.1 Overview .............................................................................................................................................. 39-1

39.2 Features ............................................................................................................................................... 39-1

39.3 Block Diagram ...................................................................................................................................... 39-2

39.4 Functional Description ......................................................................................................................... 39-3

39.4.1 Data Format of SPDIF .................................................................................................................. 39-3

39.4.2 Channel Coding ............................................................................................................................ 39-6

39.4.3 Preamble ...................................................................................................................................... 39-6

39.4.4 Non-Linear PCM-Encoded Source (IEC 61937) .......................................................................... 39-7

39.4.5 SPDIF Operation .......................................................................................................................... 39-9

39.4.6 Shadowed Register .................................................................................................................... 39-10

39.5 I/O Description ................................................................................................................................... 39-11

39.6 Register Description ........................................................................................................................... 39-12

39.6.1 Register Map Summary .............................................................................................................. 39-12

40 CHIP TO CHIP (C2C) ................................................................................. 40-1

40.1 Overview .............................................................................................................................................. 40-1

40.2 Clock .................................................................................................................................................... 40-3

40.3 Address Mapping ................................................................................................................................. 40-4

40.3.1 Address Mapping Overview .......................................................................................................... 40-4

40.3.2 AP EMIF Address Mapping .......................................................................................................... 40-5

40.3.3 SSCM Address Mapping .............................................................................................................. 40-7

40.4 General Purpose Signals Mapping ...................................................................................................... 40-8

40.4.1 Overview ....................................................................................................................................... 40-8

40.4.2 GENI (General Purpose INPUT) Signals ..................................................................................... 40-8

40.4.3 GENO (General Purpose Output) Signals .................................................................................... 40-8

40.5 Sleep/Wake-up Scheme ...................................................................................................................... 40-9

40.5.1 AP Wake-up Procedure and Timing ............................................................................................. 40-9

40.5.2 CP Sleep Procedure ................................................................................................................... 40-12

40.6 Reset Scheme.................................................................................................................................... 40-14

40.6.1 Reset Cases ............................................................................................................................... 40-14

40.7 Boot-up Scheme ................................................................................................................................ 40-15

40.7.1 Reset & Start-up Sequence ........................................................................................................ 40-16

40.7.2 Keeping CP in Reset State before AP Ready for C2C ............................................................... 40-16

40.8 OPP Change Scheme ........................................................................................................................ 40-17

40.8.1 Increasing ................................................................................................................................... 40-17

40.8.2 Decreasing .................................................................................................................................. 40-18

40.8.3 I/O Description ............................................................................................................................ 40-19

40.9 Register Description ........................................................................................................................... 40-20

40.9.1 Register Map Summary .............................................................................................................. 40-20

41 HIGH-SPEED SYNCHRONOUS SERIAL INTERFACE (HSI) ................... 41-1

41.1 Overview .............................................................................................................................................. 41-1

41.2 Features ............................................................................................................................................... 41-1

41.3 Functional Description ......................................................................................................................... 41-2

41.3.1 Block Diagram .............................................................................................................................. 41-2

41.3.2 Interface Port Description ............................................................................................................. 41-4

41.3.3 Programming Basic Sequence Guide .......................................................................................... 41-5

41.4 Register Description ........................................................................................................................... 41-11

41.4.1 Register Map Summary .............................................................................................................. 41-11

42 DISPLAY CONTROLLER .......................................................................... 42-1

42.1 Overview .............................................................................................................................................. 42-1

42.2 Features of Display Controller ............................................................................................................. 42-2

42.3 Functional Description ......................................................................................................................... 42-4

42.3.1 Brief Description of the Sub-Block ................................................................................................ 42-4

42.3.2 Data Flow ...................................................................................................................................... 42-5

42.3.3 Overview of the Color Data .......................................................................................................... 42-8

42.3.4 Color Space Conversion ............................................................................................................. 42-23

42.3.5 Palette Usage ............................................................................................................................. 42-25

42.3.6 Window Blending ........................................................................................................................ 42-28

42.3.7 Image Enhancement .................................................................................................................. 42-37

42.3.8 VTIME Controller Operation ....................................................................................................... 42-44

42.3.9 Setting of Commands ................................................................................................................. 42-47

42.3.10 Virtual Display ........................................................................................................................... 42-50

42.3.11 RGB Interface Specification ..................................................................................................... 42-51

42.3.12 LCD Indirect i80 System Interface ............................................................................................ 42-60

42.4 I/O Description ................................................................................................................................... 42-64

42.5 Register Description ........................................................................................................................... 42-65

42.5.1 Register Map Summary .............................................................................................................. 42-66

42.5.2 Palette Memory ........................................................................................................................... 42-72

42.5.3 Control Register .......................................................................................................................... 42-73

42.5.4 Gamma Lookup Table .............................................................................................................. 42-145

42.5.5 Shadow Windows Control ........................................................................................................ 42-146

42.5.6 Palette Ram .............................................................................................................................. 42-147

43 CAMERA INTERFACE AND SCALER ...................................................... 43-1

43.1 Overview .............................................................................................................................................. 43-1

43.2 Features of CAMIF ............................................................................................................................... 43-3

43.3 External Interface ................................................................................................................................. 43-5

43.4 Timing Diagram and Data Alignment of Camera ................................................................................. 43-6

43.4.1 Timing Diagram of ITU Camera .................................................................................................... 43-6

43.4.2 MIPI CSI Data Alignment from MIPI Camera ............................................................................. 43-10

43.5 External Connection Guide ................................................................................................................ 43-11

43.6 Camera Interface Operation .............................................................................................................. 43-12

43.6.1 Input/Output DMA Ports ............................................................................................................. 43-12

43.6.2 Clock Domain ............................................................................................................................. 43-13

43.6.3 Frame Memory Hierarchy ........................................................................................................... 43-14

43.6.4 Memory Storing Method ............................................................................................................. 43-15

43.6.5 Timing Diagram for Register Setting .......................................................................................... 43-16

43.6.6 Timing Diagram for last IRQ ....................................................................................................... 43-18

43.6.7 Timing Diagram for IRQ (Memory Data Scaling Mode).............................................................. 43-20

43.6.8 Input DMA Feature ..................................................................................................................... 43-21

43.6.9 Camera Interlace Input Support ................................................................................................. 43-22

43.7 Input/Output Description .................................................................................................................... 43-23

43.8 Register Description ........................................................................................................................... 43-24

43.8.1 Register Map Summary .............................................................................................................. 43-24

44 FIMC_LITE (CAMERA INTERFACE) ........................................................ 44-1

44.1 Overview of Camera Interface in FIMC_LITE ...................................................................................... 44-1

44.1.1 Block Diagram .............................................................................................................................. 44-1

44.2 Timing Diagram and Data Alignment of Camera ................................................................................. 44-2

44.2.1 Parallel INTERFACE .................................................................................................................... 44-2

44.2.2 MIPI CSI Slave Interface .............................................................................................................. 44-3

44.2.3 Local Output Interface Data Alignment ........................................................................................ 44-4

44.3 External Connection Guide .................................................................................................................. 44-5

44.4 Input / Output Path ............................................................................................................................... 44-6

44.5 I/O Description ..................................................................................................................................... 44-7

44.6 Register Description ............................................................................................................................. 44-8

44.6.1 Register Map ................................................................................................................................ 44-8

45 MIPI-DSI MASTER .................................................................................... 45-1

45.1 Overview .............................................................................................................................................. 45-1

45.2 Features ............................................................................................................................................... 45-1

45.2.1 Block Diagram .............................................................................................................................. 45-2

45.2.2 Interfaces and Protocol ................................................................................................................. 45-6

45.2.3 Configuration .............................................................................................................................. 45-16

45.2.4 Dual Display versus Single Display ............................................................................................ 45-17

45.2.5 PLL ............................................................................................................................................. 45-18

45.2.6 Buffer .......................................................................................................................................... 45-18

45.3 I/O Description ................................................................................................................................... 45-19

45.4 Register Description ........................................................................................................................... 45-20

45.4.1 Register Map Summary .............................................................................................................. 45-20

45.5 DPHY PLL Control ............................................................................................................................. 45-39

45.5.1 PMS Setting Sample for MIPI PLL ............................................................................................. 45-39

46 MIPI-CSI SLAVE (MIPI-CSI) ...................................................................... 46-1

46.1 Overview of MIPI CSIS ........................................................................................................................ 46-1

46.2 Features ............................................................................................................................................... 46-1

46.3 Block Diagram ...................................................................................................................................... 46-2

46.4 Interface and Protocol .......................................................................................................................... 46-3

46.5 Data Format ......................................................................................................................................... 46-4

46.5.1 Data Alignment ............................................................................................................................. 46-4

46.5.2 YUV422 8-bit Order ...................................................................................................................... 46-4

46.6 I/O Description ..................................................................................................................................... 46-5

46.7 Register Description ............................................................................................................................. 46-6

46.7.1 Register Map Summary ................................................................................................................ 46-6

47 2D GRAPHIC ACCELERATOR ................................................................. 47-1

47.1 Overview .............................................................................................................................................. 47-1

47.2 Features ............................................................................................................................................... 47-2

47.2.1 Host Interface ............................................................................................................................... 47-2

47.2.2 Primitives ...................................................................................................................................... 47-2

47.2.3 Per-pixel Operation ....................................................................................................................... 47-3

47.2.4 Data Format .................................................................................................................................. 47-3

47.3 Host Interface: DMA Mode ................................................................................................................... 47-4

47.4 Color Format Conversion ..................................................................................................................... 47-9

47.4.1 RGBA Format ............................................................................................................................... 47-9

47.5 Rendering Pipeline ............................................................................................................................. 47-11

47.5.1 Primitive Drawing ........................................................................................................................ 47-12

47.5.2 Rotation and Addressing Direction (Flip) .................................................................................... 47-15

47.5.3 Clipping ....................................................................................................................................... 47-17

47.5.4 Color Key .................................................................................................................................... 47-18

47.5.5 Raster Operation ........................................................................................................................ 47-19

47.5.6 Mask Operation .......................................................................................................................... 47-21

47.5.7 Alpha Blending............................................................................................................................ 47-22

47.5.8 Fast Solid Color Fill..................................................................................................................... 47-26

47.6 Register Description ........................................................................................................................... 47-27

47.6.1 Register Map Summary .............................................................................................................. 47-27

47.6.2 General Registers ....................................................................................................................... 47-31

47.6.3 Command Registers ................................................................................................................... 47-37

47.6.4 Parameter Setting Registers ...................................................................................................... 47-43

47.6.5 Source ........................................................................................................................................ 47-45

47.6.6 Destination .................................................................................................................................. 47-50

47.6.7 Pattern ........................................................................................................................................ 47-54

47.6.8 Mask ........................................................................................................................................... 47-56

47.6.9 Clipping Window ......................................................................................................................... 47-60

47.6.10 ROP & Alpha Setting ................................................................................................................ 47-62

47.6.11 Color ......................................................................................................................................... 47-63

47.6.12 Color Key .................................................................................................................................. 47-65

47.6.13 Gamma Table ........................................................................................................................... 47-68

48 3D GRAPHIC ACCELERATOR (G3D) ...................................................... 48-1

48.1 Overview of G3D .................................................................................................................................. 48-1

48.2 Features of G3D................................................................................................................................... 48-2

48.3 Architecture Brief of G3D ..................................................................................................................... 48-3

48.4 G3D Structure ...................................................................................................................................... 48-4

48.5 GPU Hardware Architecture ................................................................................................................ 48-5

48.5.1 Top-level System .......................................................................................................................... 48-5

48.5.2 Functional Block Diagram of GPU Hardware Architecture ........................................................... 48-6

48.5.3 PMU Hardware Architecture ......................................................................................................... 48-8

48.5.4 Level 2 Cache Controller Hardware Architecture ......................................................................... 48-9

49 IMAGE ROTATOR ..................................................................................... 49-1

49.1 Overview of Image Rotator .................................................................................................................. 49-1

49.2 Features of Image Rotator ................................................................................................................... 49-1

49.3 Block Diagram ...................................................................................................................................... 49-2

49.4 Supported Image Rotation Functions .................................................................................................. 49-3

49.5 Image Rotation with Windows Offset ................................................................................................... 49-4

49.6 Programming Guide ............................................................................................................................. 49-5

49.6.1 Resister Setting ............................................................................................................................ 49-5

49.6.2 Restrictions on the Image Size ..................................................................................................... 49-5

49.7 Register Description ............................................................................................................................. 49-6

49.7.1 Register Map Summary ................................................................................................................ 49-6

50 JPEG CODEC ............................................................................................ 50-1

50.1 Overview .............................................................................................................................................. 50-1

50.2 Features ............................................................................................................................................... 50-2

50.3 Functional Description ......................................................................................................................... 50-4

50.3.1 Encoder Flow ................................................................................................................................ 50-4

50.3.2 Decoder Flow ................................................................................................................................ 50-6

50.3.3 Color Component Data Ordering .................................................................................................. 50-7

50.4 Programmer's Model ............................................................................................................................ 50-8

50.4.1 Encoder Flow Chart ...................................................................................................................... 50-8

50.4.2 Decoder Flow Chart ...................................................................................................................... 50-9

50.5 Register Description ........................................................................................................................... 50-10

50.5.1 Register Map Summary .............................................................................................................. 50-10

50.5.2 Programming QUAN_TBL_ENT and HUFF_TBL_ENT ............................................................. 50-26

50.6 Example Codes .................................................................................................................................. 50-28

剩余2857页未读，继续阅读

数学渣渣

粉丝: 5

Exynos4412微处理器用户手册详解

三星Exynos 4412完整用户手册和FS4412原理图

（4412手册完整版）SEC_Exynos 4412 SCP_Users Manual

Cotex-A9中文数据手册

Exynos4412用户手册.rar

三星Exynos4412使用手册 Cortex-A9使用手册

Exynos4412用户手册（2858页）

Exynos4412用户手册 （英文版）

Exynos 4412用户手册（原厂带）

Exynos4412用户手册详尽指南

Exynos4412用户手册解压与功能概述

最新资源

Exynos4412用户手册（英文版）